Lines Matching +full:imx51 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
19 * pre-existing /chosen node to be available to insert the
53 #address-cells = <1>;
54 #size-cells = <0>;
56 idle-states {
57 entry-method = "psci";
59 cpu_sleep_wait: cpu-sleep-wait {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x0010000>;
62 local-timer-stop;
63 entry-latency-us = <100>;
64 exit-latency-us = <50>;
65 min-residency-us = <1000>;
70 compatible = "arm,cortex-a7";
73 clock-frequency = <792000000>;
74 clock-latency = <61036>; /* two CLK32 periods */
76 cpu-idle-states = <&cpu_sleep_wait>;
80 ckil: clock-cki {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
87 osc: clock-osc {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
95 compatible = "usb-nop-xceiv";
97 clock-names = "main_clk";
98 #phy-cells = <0>;
102 compatible = "usb-nop-xceiv";
104 clock-names = "main_clk";
105 #phy-cells = <0>;
109 compatible = "arm,cortex-a7-pmu";
110 interrupt-parent = <&gpc>;
112 interrupt-affinity = <&cpu0>;
117 * non-configurable replicators don't show up on the
120 compatible = "arm,coresight-static-replicator";
122 out-ports {
123 #address-cells = <1>;
124 #size-cells = <0>;
129 remote-endpoint = <&tpiu_in_port>;
136 remote-endpoint = <&etr_in_port>;
141 in-ports {
144 remote-endpoint = <&etf_out_port>;
151 compatible = "arm,armv7-timer";
152 interrupt-parent = <&intc>;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "simple-bus";
163 interrupt-parent = <&gpc>;
167 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
170 clock-names = "apb_pclk";
172 ca_funnel_in_ports: in-ports {
175 remote-endpoint = <&etm0_out_port>;
182 out-ports {
185 remote-endpoint = <&hugo_funnel_in_port0>;
193 compatible = "arm,coresight-etm3x", "arm,primecell";
197 clock-names = "apb_pclk";
199 out-ports {
202 remote-endpoint = <&ca_funnel_in_port0>;
209 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
212 clock-names = "apb_pclk";
214 in-ports {
215 #address-cells = <1>;
216 #size-cells = <0>;
221 remote-endpoint = <&ca_funnel_out_port0>;
234 out-ports {
237 remote-endpoint = <&etf_in_port>;
244 compatible = "arm,coresight-tmc", "arm,primecell";
247 clock-names = "apb_pclk";
249 in-ports {
252 remote-endpoint = <&hugo_funnel_out_port0>;
257 out-ports {
260 remote-endpoint = <&replicator_in_port0>;
267 compatible = "arm,coresight-tmc", "arm,primecell";
270 clock-names = "apb_pclk";
272 in-ports {
275 remote-endpoint = <&replicator_out_port1>;
282 compatible = "arm,coresight-tpiu", "arm,primecell";
285 clock-names = "apb_pclk";
287 in-ports {
290 remote-endpoint = <&replicator_out_port0>;
296 intc: interrupt-controller@31001000 {
297 compatible = "arm,cortex-a7-gic";
299 #interrupt-cells = <3>;
300 interrupt-controller;
301 interrupt-parent = <&intc>;
309 compatible = "fsl,aips-bus", "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
316 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
328 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 gpio-ranges = <&iomuxc 0 13 32>;
340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 gpio-ranges = <&iomuxc 0 45 29>;
352 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 74 24>;
364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 gpio-ranges = <&iomuxc 0 98 18>;
376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <&iomuxc 0 116 23>;
388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 139 16>;
400 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
407 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
415 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
423 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
430 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
431 compatible = "fsl,imx7d-iomuxc-lpsr";
433 fsl,input-sel = <&iomuxc>;
437 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
442 clock-names = "ipg", "per";
446 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
451 clock-names = "ipg", "per";
456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
461 clock-names = "ipg", "per";
466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
471 clock-names = "ipg", "per";
476 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
484 compatible = "fsl,imx7d-iomuxc";
488 gpr: iomuxc-gpr@30340000 {
489 compatible = "fsl,imx7d-iomuxc-gpr",
490 "fsl,imx6q-iomuxc-gpr", "syscon",
491 "simple-mfd";
494 mux: mux-controller {
495 compatible = "mmio-mux";
496 #mux-control-cells = <0>;
497 mux-reg-masks = <0x14 0x00000010>;
500 video_mux: csi-mux {
501 compatible = "video-mux";
502 mux-controls = <&mux 0>;
503 #address-cells = <1>;
504 #size-cells = <0>;
515 remote-endpoint = <&mipi_vc0_to_csi_mux>;
523 remote-endpoint = <&csi_from_csi_mux>;
530 #address-cells = <1>;
531 #size-cells = <1>;
532 compatible = "fsl,imx7d-ocotp", "syscon";
540 fuse_grade: fuse-grade@10 {
546 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
547 "syscon", "simple-mfd";
552 reg_1p0d: regulator-vdd1p0d {
553 compatible = "fsl,anatop-regulator";
554 regulator-name = "vdd1p0d";
555 regulator-min-microvolt = <800000>;
556 regulator-max-microvolt = <1200000>;
557 anatop-reg-offset = <0x210>;
558 anatop-vol-bit-shift = <8>;
559 anatop-vol-bit-width = <5>;
560 anatop-min-bit-val = <8>;
561 anatop-min-voltage = <800000>;
562 anatop-max-voltage = <1200000>;
563 anatop-enable-bit = <0>;
566 reg_1p2: regulator-vdd1p2 {
567 compatible = "fsl,anatop-regulator";
568 regulator-name = "vdd1p2";
569 regulator-min-microvolt = <1100000>;
570 regulator-max-microvolt = <1300000>;
571 anatop-reg-offset = <0x220>;
572 anatop-vol-bit-shift = <8>;
573 anatop-vol-bit-width = <5>;
574 anatop-min-bit-val = <0x14>;
575 anatop-min-voltage = <1100000>;
576 anatop-max-voltage = <1300000>;
577 anatop-enable-bit = <0>;
581 compatible = "fsl,imx7d-tempmon";
582 interrupt-parent = <&gpc>;
585 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
586 nvmem-cell-names = "calib", "temp_grade";
592 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
595 snvs_rtc: snvs-rtc-lp {
596 compatible = "fsl,sec-v4.0-mon-rtc-lp";
602 clock-names = "snvs-rtc";
605 snvs_pwrkey: snvs-powerkey {
606 compatible = "fsl,sec-v4.0-pwrkey";
610 clock-names = "snvs-pwrkey";
612 wakeup-source;
617 clks: clock-controller@30380000 {
618 compatible = "fsl,imx7d-ccm";
622 #clock-cells = <1>;
624 clock-names = "ckil", "osc";
627 src: reset-controller@30390000 {
628 compatible = "fsl,imx7d-src", "syscon";
631 #reset-cells = <1>;
635 compatible = "fsl,imx7d-gpc";
637 interrupt-controller;
639 #interrupt-cells = <3>;
640 interrupt-parent = <&intc>;
641 #power-domain-cells = <1>;
644 #address-cells = <1>;
645 #size-cells = <0>;
647 pgc_mipi_phy: power-domain@0 {
648 #power-domain-cells = <0>;
650 power-supply = <®_1p0d>;
653 pgc_pcie_phy: power-domain@1 {
654 #power-domain-cells = <0>;
656 power-supply = <®_1p0d>;
659 pgc_hsic_phy: power-domain@2 {
660 #power-domain-cells = <0>;
662 power-supply = <®_1p2>;
669 compatible = "fsl,aips-bus", "simple-bus";
670 #address-cells = <1>;
671 #size-cells = <1>;
676 compatible = "fsl,imx7d-adc";
680 clock-names = "adc";
681 #io-channel-cells = <1>;
686 compatible = "fsl,imx7d-adc";
690 clock-names = "adc";
691 #io-channel-cells = <1>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
703 clock-names = "ipg", "per";
708 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
713 clock-names = "ipg", "per";
714 #pwm-cells = <3>;
719 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
724 clock-names = "ipg", "per";
725 #pwm-cells = <3>;
730 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
735 clock-names = "ipg", "per";
736 #pwm-cells = <3>;
741 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
746 clock-names = "ipg", "per";
747 #pwm-cells = <3>;
752 compatible = "fsl,imx7-csi";
758 clock-names = "axi", "mclk", "dcic";
763 remote-endpoint = <&csi_mux_to_csi>;
769 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
774 clock-names = "pix", "axi";
778 mipi_csi: mipi-csi@30750000 {
779 compatible = "fsl,imx7-mipi-csi2";
781 #address-cells = <1>;
782 #size-cells = <0>;
787 clock-names = "pclk", "wrap", "phy";
788 power-domains = <&pgc_mipi_phy>;
789 phy-supply = <®_1p0d>;
791 reset-names = "mrst";
802 remote-endpoint = <&csi_mux_from_mipi_vc0>;
809 compatible = "fsl,aips-bus", "simple-bus";
810 #address-cells = <1>;
811 #size-cells = <1>;
815 spba-bus@30800000 {
816 compatible = "fsl,spba-bus", "simple-bus";
817 #address-cells = <1>;
818 #size-cells = <1>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
830 clock-names = "ipg", "per";
835 #address-cells = <1>;
836 #size-cells = <0>;
837 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
842 clock-names = "ipg", "per";
847 #address-cells = <1>;
848 #size-cells = <0>;
849 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
854 clock-names = "ipg", "per";
859 compatible = "fsl,imx7d-uart",
860 "fsl,imx6q-uart";
865 clock-names = "ipg", "per";
870 compatible = "fsl,imx7d-uart",
871 "fsl,imx6q-uart";
876 clock-names = "ipg", "per";
881 compatible = "fsl,imx7d-uart",
882 "fsl,imx6q-uart";
887 clock-names = "ipg", "per";
892 #sound-dai-cells = <0>;
893 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
900 clock-names = "bus", "mclk1", "mclk2", "mclk3";
901 dma-names = "rx", "tx";
907 #sound-dai-cells = <0>;
908 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
915 clock-names = "bus", "mclk1", "mclk2", "mclk3";
916 dma-names = "rx", "tx";
922 #sound-dai-cells = <0>;
923 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
930 clock-names = "bus", "mclk1", "mclk2", "mclk3";
931 dma-names = "rx", "tx";
938 compatible = "fsl,sec-v4.0";
939 #address-cells = <1>;
940 #size-cells = <1>;
946 clock-names = "ipg", "aclk";
949 compatible = "fsl,sec-v4.0-job-ring";
955 compatible = "fsl,sec-v4.0-job-ring";
961 compatible = "fsl,sec-v4.0-job-ring";
968 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
973 clock-names = "ipg", "per";
974 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
979 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
984 clock-names = "ipg", "per";
985 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
989 i2c1: i2c@30a20000 {
990 #address-cells = <1>;
991 #size-cells = <0>;
992 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
999 i2c2: i2c@30a30000 {
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1009 i2c3: i2c@30a40000 {
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1019 i2c4: i2c@30a50000 {
1020 #address-cells = <1>;
1021 #size-cells = <0>;
1022 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1030 compatible = "fsl,imx7d-uart",
1031 "fsl,imx6q-uart";
1036 clock-names = "ipg", "per";
1041 compatible = "fsl,imx7d-uart",
1042 "fsl,imx6q-uart";
1047 clock-names = "ipg", "per";
1052 compatible = "fsl,imx7d-uart",
1053 "fsl,imx6q-uart";
1058 clock-names = "ipg", "per";
1063 compatible = "fsl,imx7d-uart",
1064 "fsl,imx6q-uart";
1069 clock-names = "ipg", "per";
1074 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1078 #mbox-cells = <2>;
1083 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1087 #mbox-cells = <2>;
1088 fsl,mu-side-b;
1093 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1099 phy-clkgate-delay-us = <400>;
1104 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1107 power-domains = <&pgc_hsic_phy>;
1113 phy-clkgate-delay-us = <400>;
1118 #index-cells = <1>;
1119 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1124 #index-cells = <1>;
1125 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1130 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1136 clock-names = "ipg", "ahb", "per";
1137 bus-width = <4>;
1142 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1148 clock-names = "ipg", "ahb", "per";
1149 bus-width = <4>;
1154 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1160 clock-names = "ipg", "ahb", "per";
1161 bus-width = <4>;
1166 compatible = "fsl,imx7d-qspi";
1168 reg-names = "QuadSPI", "QuadSPI-memory";
1169 #address-cells = <1>;
1170 #size-cells = <0>;
1174 clock-names = "qspi_en", "qspi";
1179 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1184 clock-names = "ipg", "ahb";
1185 #dma-cells = <3>;
1186 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1190 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1192 interrupt-names = "int0", "int1", "int2", "pps";
1202 clock-names = "ipg", "ahb", "ptp",
1204 fsl,num-tx-queues = <3>;
1205 fsl,num-rx-queues = <3>;
1206 fsl,stop-mode = <&gpr 0x10 3>;
1211 dma_apbh: dma-apbh@33000000 {
1212 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1218 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1219 #dma-cells = <1>;
1220 dma-channels = <4>;
1224 gpmi: nand-controller@33002000{
1225 compatible = "fsl,imx7d-gpmi-nand";
1226 #address-cells = <1>;
1227 #size-cells = <1>;
1229 reg-names = "gpmi-nand", "bch";
1231 interrupt-names = "bch";
1234 clock-names = "gpmi_io", "gpmi_bch_apb";
1236 dma-names = "rx-tx";
1238 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1239 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;