Lines Matching +full:imx7d +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
7 #include <dt-bindings/reset/imx7-reset.h>
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
14 #cooling-cells = <2>;
15 nvmem-cells = <&fuse_grade>;
16 nvmem-cell-names = "speed_grade";
20 compatible = "arm,cortex-a7";
23 clock-frequency = <996000000>;
24 operating-points-v2 = <&cpu0_opp_table>;
25 #cooling-cells = <2>;
26 cpu-idle-states = <&cpu_sleep_wait>;
31 compatible = "arm,armv7-timer";
32 interrupt-parent = <&intc>;
39 cpu0_opp_table: opp-table {
40 compatible = "operating-points-v2";
41 opp-shared;
43 opp-792000000 {
44 opp-hz = /bits/ 64 <792000000>;
45 opp-microvolt = <1000000>;
46 clock-latency-ns = <150000>;
47 opp-supported-hw = <0xd>, <0x7>;
48 opp-suspend;
51 opp-996000000 {
52 opp-hz = /bits/ 64 <996000000>;
53 opp-microvolt = <1100000>;
54 clock-latency-ns = <150000>;
55 opp-supported-hw = <0xc>, <0x7>;
56 opp-suspend;
59 opp-1200000000 {
60 opp-hz = /bits/ 64 <1200000000>;
61 opp-microvolt = <1225000>;
62 clock-latency-ns = <150000>;
63 opp-supported-hw = <0x8>, <0x3>;
64 opp-suspend;
69 compatible = "usb-nop-xceiv";
71 clock-names = "main_clk";
72 #phy-cells = <0>;
77 compatible = "arm,coresight-etm3x", "arm,primecell";
82 * without arm,primecell-periphid because amba bus try to
85 arm,primecell-periphid = <0xbb956>;
88 clock-names = "apb_pclk";
90 out-ports {
93 remote-endpoint = <&ca_funnel_in_port1>;
99 intc: interrupt-controller@31001000 {
100 compatible = "arm,cortex-a7-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
114 pcie_phy: pcie-phy@306d0000 {
115 compatible = "fsl,imx7d-pcie-phy";
123 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
129 phy-clkgate-delay-us = <400>;
134 #index-cells = <1>;
135 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
140 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
142 interrupt-names = "int0", "int1", "int2", "pps";
152 clock-names = "ipg", "ahb", "ptp",
154 fsl,num-tx-queues = <3>;
155 fsl,num-rx-queues = <3>;
156 fsl,stop-mode = <&gpr 0x10 4>;
161 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
164 reg-names = "dbi", "config";
165 #address-cells = <3>;
166 #size-cells = <2>;
168 bus-range = <0x00 0xff>;
170 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
171 num-lanes = <1>;
172 num-viewport = <4>;
174 interrupt-names = "msi";
175 #interrupt-cells = <1>;
176 interrupt-map-mask = <0 0 0 0x7>;
181 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
188 clock-names = "pcie", "pcie_bus", "pcie_phy";
189 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
191 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
194 fsl,max-link-speed = <2>;
195 power-domains = <&pgc_pcie_phy>;
199 reset-names = "pciephy", "apps", "turnoff";
200 fsl,imx7d-pcie-phy = <&pcie_phy>;
206 #address-cells = <1>;
207 #size-cells = <0>;
212 remote-endpoint = <&etm1_out_port>;