Lines Matching full:assigned
189 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
190 assigned-clock-rates = <884736000>;
211 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
214 assigned-clock-rates = <0>, <100000000>;
294 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
297 assigned-clock-rates = <0>, <100000000>;
457 assigned-clocks = <&cs2000>;
458 assigned-clock-rates = <24000000>;
568 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
570 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
571 assigned-clock-rates = <0>, <36864000>;
578 assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>,
580 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
581 assigned-clock-rates = <0>, <36864000>;
588 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
590 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
591 assigned-clock-rates = <0>, <36864000>;
598 assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
599 assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
606 assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
607 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;