Lines Matching full:assigned
215 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
217 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
218 assigned-clock-rates = <0>, <100000000>;
242 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
244 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
245 assigned-clock-rates = <0>, <100000000>;
386 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
389 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
390 assigned-clock-rates = <0>, <884736000>, <12288000>;
422 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
425 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
426 assigned-clock-rates = <0>, <884736000>, <36864000>;
433 assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
436 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
437 assigned-clock-rates = <0>, <884736000>, <36864000>;
448 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
449 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
456 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
457 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
501 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
502 assigned-clock-rates = <400000000>;