Lines Matching +full:imx21 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6sx-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6sx-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a9";
64 next-level-cache = <&L2>;
65 operating-points = <
72 fsl,soc-operating-points = <
79 clock-latency = <61036>; /* two CLK32 periods */
80 #cooling-cells = <2>;
86 clock-names = "arm", "pll2_pfd2_396m", "step",
88 arm-supply = <®_arm>;
89 soc-supply = <®_soc>;
90 nvmem-cells = <&cpu_speed_grade>;
91 nvmem-cell-names = "speed_grade";
95 ckil: clock-ckil {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <32768>;
99 clock-output-names = "ckil";
102 osc: clock-osc {
103 compatible = "fixed-clock";
104 #clock-cells = <0>;
105 clock-frequency = <24000000>;
106 clock-output-names = "osc";
109 ipp_di0: clock-ipp-di0 {
110 compatible = "fixed-clock";
111 #clock-cells = <0>;
112 clock-frequency = <0>;
113 clock-output-names = "ipp_di0";
116 ipp_di1: clock-ipp-di1 {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <0>;
120 clock-output-names = "ipp_di1";
123 anaclk1: clock-anaclk1 {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <0>;
127 clock-output-names = "anaclk1";
130 anaclk2: clock-anaclk2 {
131 compatible = "fixed-clock";
132 #clock-cells = <0>;
133 clock-frequency = <0>;
134 clock-output-names = "anaclk2";
138 compatible = "fsl,imx6sx-mqs";
144 compatible = "arm,cortex-a9-pmu";
145 interrupt-parent = <&gpc>;
150 compatible = "usb-nop-xceiv";
151 #phy-cells = <0>;
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gpc>;
162 compatible = "mmio-sram";
168 compatible = "mmio-sram";
173 intc: interrupt-controller@a01000 {
174 compatible = "arm,cortex-a9-gic";
175 #interrupt-cells = <3>;
176 interrupt-controller;
179 interrupt-parent = <&intc>;
182 L2: cache-controller@a02000 {
183 compatible = "arm,pl310-cache";
186 cache-unified;
187 cache-level = <2>;
188 arm,tag-latency = <4 2 3>;
189 arm,data-latency = <4 2 3>;
199 clock-names = "bus", "core", "shader";
200 power-domains = <&pd_pu>;
203 dma_apbh: dma-apbh@1804000 {
204 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
210 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
211 #dma-cells = <1>;
212 dma-channels = <4>;
216 gpmi: nand-controller@1806000{
217 compatible = "fsl,imx6sx-gpmi-nand";
218 #address-cells = <1>;
219 #size-cells = <1>;
221 reg-names = "gpmi-nand", "bch";
223 interrupt-names = "bch";
229 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
232 dma-names = "rx-tx";
237 compatible = "fsl,aips-bus", "simple-bus";
238 #address-cells = <1>;
239 #size-cells = <1>;
243 spba-bus@2000000 {
244 compatible = "fsl,spba-bus", "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
251 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
256 dma-names = "rx", "tx";
264 clock-names = "core", "rxtx0",
273 #address-cells = <1>;
274 #size-cells = <0>;
275 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
280 clock-names = "ipg", "per";
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
292 clock-names = "ipg", "per";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
304 clock-names = "ipg", "per";
309 #address-cells = <1>;
310 #size-cells = <0>;
311 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
316 clock-names = "ipg", "per";
321 compatible = "fsl,imx6sx-uart",
322 "fsl,imx6q-uart", "fsl,imx21-uart";
327 clock-names = "ipg", "per";
329 dma-names = "rx", "tx";
334 compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
342 clock-names = "core", "mem", "extal",
346 dma-names = "rx", "tx";
351 #sound-dai-cells = <0>;
352 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
357 clock-names = "ipg", "baud";
359 dma-names = "rx", "tx";
360 fsl,fifo-depth = <15>;
365 #sound-dai-cells = <0>;
366 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
371 clock-names = "ipg", "baud";
373 dma-names = "rx", "tx";
374 fsl,fifo-depth = <15>;
379 #sound-dai-cells = <0>;
380 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
385 clock-names = "ipg", "baud";
387 dma-names = "rx", "tx";
388 fsl,fifo-depth = <15>;
393 compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
403 clock-names = "mem", "ipg", "asrck_0",
411 dma-names = "rxa", "rxb", "rxc",
413 fsl,asrc-rate = <48000>;
414 fsl,asrc-width = <16>;
420 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
425 clock-names = "ipg", "per";
426 #pwm-cells = <3>;
430 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
435 clock-names = "ipg", "per";
436 #pwm-cells = <3>;
440 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
445 clock-names = "ipg", "per";
446 #pwm-cells = <3>;
450 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
455 clock-names = "ipg", "per";
456 #pwm-cells = <3>;
460 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
465 clock-names = "ipg", "per";
466 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
471 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
476 clock-names = "ipg", "per";
477 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
482 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
487 clock-names = "ipg", "per";
491 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
495 gpio-controller;
496 #gpio-cells = <2>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 gpio-ranges = <&iomuxc 0 5 26>;
503 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
507 gpio-controller;
508 #gpio-cells = <2>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 gpio-ranges = <&iomuxc 0 31 20>;
515 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
519 gpio-controller;
520 #gpio-cells = <2>;
521 interrupt-controller;
522 #interrupt-cells = <2>;
523 gpio-ranges = <&iomuxc 0 51 29>;
527 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupt-controller;
534 #interrupt-cells = <2>;
535 gpio-ranges = <&iomuxc 0 80 32>;
539 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
543 gpio-controller;
544 #gpio-cells = <2>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 gpio-ranges = <&iomuxc 0 112 24>;
551 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
555 gpio-controller;
556 #gpio-cells = <2>;
557 interrupt-controller;
558 #interrupt-cells = <2>;
559 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
563 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
567 gpio-controller;
568 #gpio-cells = <2>;
569 interrupt-controller;
570 #interrupt-cells = <2>;
571 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
575 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
583 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
590 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
597 clks: clock-controller@20c4000 {
598 compatible = "fsl,imx6sx-ccm";
602 #clock-cells = <1>;
604 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
608 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
609 "syscon", "simple-mfd";
615 reg_vdd1p1: regulator-1p1 {
616 compatible = "fsl,anatop-regulator";
617 regulator-name = "vdd1p1";
618 regulator-min-microvolt = <1000000>;
619 regulator-max-microvolt = <1200000>;
620 regulator-always-on;
621 anatop-reg-offset = <0x110>;
622 anatop-vol-bit-shift = <8>;
623 anatop-vol-bit-width = <5>;
624 anatop-min-bit-val = <4>;
625 anatop-min-voltage = <800000>;
626 anatop-max-voltage = <1375000>;
627 anatop-enable-bit = <0>;
630 reg_vdd3p0: regulator-3p0 {
631 compatible = "fsl,anatop-regulator";
632 regulator-name = "vdd3p0";
633 regulator-min-microvolt = <2800000>;
634 regulator-max-microvolt = <3150000>;
635 regulator-always-on;
636 anatop-reg-offset = <0x120>;
637 anatop-vol-bit-shift = <8>;
638 anatop-vol-bit-width = <5>;
639 anatop-min-bit-val = <0>;
640 anatop-min-voltage = <2625000>;
641 anatop-max-voltage = <3400000>;
642 anatop-enable-bit = <0>;
645 reg_vdd2p5: regulator-2p5 {
646 compatible = "fsl,anatop-regulator";
647 regulator-name = "vdd2p5";
648 regulator-min-microvolt = <2250000>;
649 regulator-max-microvolt = <2750000>;
650 regulator-always-on;
651 anatop-reg-offset = <0x130>;
652 anatop-vol-bit-shift = <8>;
653 anatop-vol-bit-width = <5>;
654 anatop-min-bit-val = <0>;
655 anatop-min-voltage = <2100000>;
656 anatop-max-voltage = <2875000>;
657 anatop-enable-bit = <0>;
660 reg_arm: regulator-vddcore {
661 compatible = "fsl,anatop-regulator";
662 regulator-name = "vddarm";
663 regulator-min-microvolt = <725000>;
664 regulator-max-microvolt = <1450000>;
665 regulator-always-on;
666 anatop-reg-offset = <0x140>;
667 anatop-vol-bit-shift = <0>;
668 anatop-vol-bit-width = <5>;
669 anatop-delay-reg-offset = <0x170>;
670 anatop-delay-bit-shift = <24>;
671 anatop-delay-bit-width = <2>;
672 anatop-min-bit-val = <1>;
673 anatop-min-voltage = <725000>;
674 anatop-max-voltage = <1450000>;
677 reg_pcie: regulator-vddpcie {
678 compatible = "fsl,anatop-regulator";
679 regulator-name = "vddpcie";
680 regulator-min-microvolt = <725000>;
681 regulator-max-microvolt = <1450000>;
682 anatop-reg-offset = <0x140>;
683 anatop-vol-bit-shift = <9>;
684 anatop-vol-bit-width = <5>;
685 anatop-delay-reg-offset = <0x170>;
686 anatop-delay-bit-shift = <26>;
687 anatop-delay-bit-width = <2>;
688 anatop-min-bit-val = <1>;
689 anatop-min-voltage = <725000>;
690 anatop-max-voltage = <1450000>;
693 reg_soc: regulator-vddsoc {
694 compatible = "fsl,anatop-regulator";
695 regulator-name = "vddsoc";
696 regulator-min-microvolt = <725000>;
697 regulator-max-microvolt = <1450000>;
698 regulator-always-on;
699 anatop-reg-offset = <0x140>;
700 anatop-vol-bit-shift = <18>;
701 anatop-vol-bit-width = <5>;
702 anatop-delay-reg-offset = <0x170>;
703 anatop-delay-bit-shift = <28>;
704 anatop-delay-bit-width = <2>;
705 anatop-min-bit-val = <1>;
706 anatop-min-voltage = <725000>;
707 anatop-max-voltage = <1450000>;
711 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
712 interrupt-parent = <&gpc>;
715 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
716 nvmem-cell-names = "calib", "temp_grade";
722 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
730 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
738 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
741 snvs_rtc: snvs-rtc-lp {
742 compatible = "fsl,sec-v4.0-mon-rtc-lp";
748 snvs_poweroff: snvs-poweroff {
749 compatible = "syscon-poweroff";
757 snvs_pwrkey: snvs-powerkey {
758 compatible = "fsl,sec-v4.0-pwrkey";
762 wakeup-source;
777 src: reset-controller@20d8000 {
778 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
782 #reset-cells = <1>;
786 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
788 interrupt-controller;
789 #interrupt-cells = <3>;
791 interrupt-parent = <&intc>;
793 clock-names = "ipg";
796 #address-cells = <1>;
797 #size-cells = <0>;
799 power-domain@0 {
801 #power-domain-cells = <0>;
804 pd_pu: power-domain@1 {
806 #power-domain-cells = <0>;
807 power-supply = <®_soc>;
811 pd_disp: power-domain@2 {
813 #power-domain-cells = <0>;
823 pd_pci: power-domain@3 {
825 #power-domain-cells = <0>;
826 power-supply = <®_pcie>;
832 compatible = "fsl,imx6sx-iomuxc";
836 gpr: iomuxc-gpr@20e4000 {
837 compatible = "fsl,imx6sx-iomuxc-gpr",
838 "fsl,imx6q-iomuxc-gpr", "syscon";
843 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
848 clock-names = "ipg", "ahb";
849 #dma-cells = <3>;
851 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
856 compatible = "fsl,aips-bus", "simple-bus";
857 #address-cells = <1>;
858 #size-cells = <1>;
863 compatible = "fsl,sec-v4.0";
864 #address-cells = <1>;
865 #size-cells = <1>;
868 interrupt-parent = <&intc>;
873 clock-names = "mem", "aclk", "ipg", "emi_slow";
876 compatible = "fsl,sec-v4.0-job-ring";
882 compatible = "fsl,sec-v4.0-job-ring";
889 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
896 ahb-burst-config = <0x0>;
897 tx-burst-size-dword = <0x10>;
898 rx-burst-size-dword = <0x10>;
903 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
909 ahb-burst-config = <0x0>;
910 tx-burst-size-dword = <0x10>;
911 rx-burst-size-dword = <0x10>;
916 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
925 ahb-burst-config = <0x0>;
926 tx-burst-size-dword = <0x10>;
927 rx-burst-size-dword = <0x10>;
932 #index-cells = <1>;
933 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
939 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
941 interrupt-names = "int0", "pps";
949 clock-names = "ipg", "ahb", "ptp",
951 fsl,num-tx-queues = <3>;
952 fsl,num-rx-queues = <3>;
953 fsl,stop-mode = <&gpr 0x10 3>;
967 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
973 clock-names = "ipg", "ahb", "per";
974 bus-width = <4>;
979 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
985 clock-names = "ipg", "ahb", "per";
986 bus-width = <4>;
991 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
997 clock-names = "ipg", "ahb", "per";
998 bus-width = <4>;
1003 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
1009 clock-names = "ipg", "ahb", "per";
1010 bus-width = <4>;
1014 i2c1: i2c@21a0000 {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1024 i2c2: i2c@21a4000 {
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1034 i2c3: i2c@21a8000 {
1035 #address-cells = <1>;
1036 #size-cells = <0>;
1037 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1044 memory-controller@21b0000 {
1045 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
1051 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
1053 interrupt-names = "int0", "pps";
1061 clock-names = "ipg", "ahb", "ptp",
1063 fsl,stop-mode = <&gpr 0x10 4>;
1068 #address-cells = <2>;
1069 #size-cells = <1>;
1070 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
1074 fsl,weim-cs-gpr = <&gpr>;
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 compatible = "fsl,imx6sx-ocotp", "syscon";
1085 cpu_speed_grade: speed-grade@10 {
1093 tempmon_temp_grade: temp-grade@20 {
1099 compatible = "fsl,imx6sx-sai";
1105 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1106 dma-names = "rx", "tx";
1112 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
1118 compatible = "fsl,imx6sx-sai";
1124 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1125 dma-names = "rx", "tx";
1131 #address-cells = <1>;
1132 #size-cells = <0>;
1133 compatible = "fsl,imx6sx-qspi";
1135 reg-names = "QuadSPI", "QuadSPI-memory";
1139 clock-names = "qspi_en", "qspi";
1144 #address-cells = <1>;
1145 #size-cells = <0>;
1146 compatible = "fsl,imx6sx-qspi";
1148 reg-names = "QuadSPI", "QuadSPI-memory";
1152 clock-names = "qspi_en", "qspi";
1157 compatible = "fsl,imx6sx-uart",
1158 "fsl,imx6q-uart", "fsl,imx21-uart";
1163 clock-names = "ipg", "per";
1165 dma-names = "rx", "tx";
1170 compatible = "fsl,imx6sx-uart",
1171 "fsl,imx6q-uart", "fsl,imx21-uart";
1176 clock-names = "ipg", "per";
1178 dma-names = "rx", "tx";
1183 compatible = "fsl,imx6sx-uart",
1184 "fsl,imx6q-uart", "fsl,imx21-uart";
1189 clock-names = "ipg", "per";
1191 dma-names = "rx", "tx";
1196 compatible = "fsl,imx6sx-uart",
1197 "fsl,imx6q-uart", "fsl,imx21-uart";
1202 clock-names = "ipg", "per";
1204 dma-names = "rx", "tx";
1208 i2c4: i2c@21f8000 {
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1211 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1220 compatible = "fsl,aips-bus", "simple-bus";
1221 #address-cells = <1>;
1222 #size-cells = <1>;
1226 spba-bus@2240000 {
1227 compatible = "fsl,spba-bus", "simple-bus";
1228 #address-cells = <1>;
1229 #size-cells = <1>;
1239 clock-names = "disp-axi", "csi_mclk", "dcic";
1244 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
1248 clock-names = "axi";
1249 power-domains = <&pd_disp>;
1259 clock-names = "disp-axi", "csi_mclk", "dcic";
1264 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1270 clock-names = "pix", "axi", "disp_axi";
1271 power-domains = <&pd_disp>;
1276 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
1282 clock-names = "pix", "axi", "disp_axi";
1283 power-domains = <&pd_disp>;
1289 reg-names = "vadc-vafe", "vadc-vdec";
1292 clock-names = "vadc", "csi";
1293 power-domains = <&pd_disp>;
1299 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1303 clock-names = "adc";
1304 fsl,adck-max-frequency = <30000000>, <40000000>,
1310 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1314 clock-names = "adc";
1315 fsl,adck-max-frequency = <30000000>, <40000000>,
1321 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1329 #address-cells = <1>;
1330 #size-cells = <0>;
1331 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1336 clock-names = "ipg", "per";
1341 compatible = "fsl,imx6sx-uart",
1342 "fsl,imx6q-uart", "fsl,imx21-uart";
1347 clock-names = "ipg", "per";
1349 dma-names = "rx", "tx";
1354 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1359 clock-names = "ipg", "per";
1360 #pwm-cells = <3>;
1364 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1369 clock-names = "ipg", "per";
1370 #pwm-cells = <3>;
1374 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1379 clock-names = "ipg", "per";
1380 #pwm-cells = <3>;
1384 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1389 clock-names = "ipg", "per";
1390 #pwm-cells = <3>;
1395 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1397 reg-names = "dbi", "config";
1398 #address-cells = <3>;
1399 #size-cells = <2>;
1401 bus-range = <0x00 0xff>;
1403 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
1404 num-lanes = <1>;
1406 interrupt-names = "msi";
1407 #interrupt-cells = <1>;
1408 interrupt-map-mask = <0 0 0 0x7>;
1409 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1417 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
1418 power-domains = <&pd_disp>, <&pd_pci>;
1419 power-domain-names = "pcie", "pcie_phy";