Lines Matching +full:imx6q +full:- +full:gpc
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright 2017-2018 NXP.
8 #include <dt-bindings/clock/imx6sll-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx6sll-pinfunc.h"
14 #address-cells = <1>;
15 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
52 operating-points = <
59 fsl,soc-operating-points = <
60 /* ARM kHz SOC-PU uV */
66 clock-latency = <61036>; /* two CLK32 periods */
67 #cooling-cells = <2>;
73 clock-names = "arm", "pll2_pfd2_396m", "step",
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
80 ckil: clock-ckil {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <32768>;
84 clock-output-names = "ckil";
87 osc: clock-osc-24m {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <24000000>;
91 clock-output-names = "osc";
94 ipp_di0: clock-ipp-di0 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <0>;
98 clock-output-names = "ipp_di0";
101 ipp_di1: clock-ipp-di1 {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <0>;
105 clock-output-names = "ipp_di1";
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&gpc>;
116 compatible = "mmio-sram";
120 intc: interrupt-controller@a01000 {
121 compatible = "arm,cortex-a9-gic";
122 #interrupt-cells = <3>;
123 interrupt-controller;
126 interrupt-parent = <&intc>;
129 L2: cache-controller@a02000 {
130 compatible = "arm,pl310-cache";
133 cache-unified;
134 cache-level = <2>;
135 arm,tag-latency = <4 2 3>;
136 arm,data-latency = <4 2 3>;
140 compatible = "fsl,aips-bus", "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
146 spba: spba-bus@2000000 {
147 compatible = "fsl,spba-bus", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
154 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
158 dma-names = "rx", "tx";
169 clock-names = "core", "rxtx0",
178 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
182 dma-names = "rx", "tx";
185 clock-names = "ipg", "per";
190 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
194 dma-names = "rx", "tx";
197 clock-names = "ipg", "per";
202 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
206 dma-names = "rx", "tx";
209 clock-names = "ipg", "per";
214 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
218 dma-names = "rx", "tx";
221 clock-names = "ipg", "per";
226 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
227 "fsl,imx21-uart";
231 dma-names = "rx", "tx";
234 clock-names = "ipg", "per";
239 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
240 "fsl,imx21-uart";
244 dma-names = "rx", "tx";
247 clock-names = "ipg", "per";
252 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
253 "fsl,imx21-uart";
257 dma-names = "rx", "tx";
260 clock-names = "ipg", "per";
265 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
269 dma-names = "rx", "tx";
270 fsl,fifo-depth = <15>;
273 clock-names = "ipg", "baud";
278 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
282 dma-names = "rx", "tx";
283 fsl,fifo-depth = <15>;
286 clock-names = "ipg", "baud";
291 compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi";
295 dma-names = "rx", "tx";
296 fsl,fifo-depth = <15>;
299 clock-names = "ipg", "baud";
304 compatible = "fsl,imx6sl-uart", "fsl,imx6q-uart",
305 "fsl,imx21-uart";
309 dma-name = "rx", "tx";
312 clock-names = "ipg", "per";
318 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
323 clock-names = "ipg", "per";
324 #pwm-cells = <3>;
328 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
333 clock-names = "ipg", "per";
334 #pwm-cells = <3>;
338 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
343 clock-names = "ipg", "per";
344 #pwm-cells = <3>;
348 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
353 clock-names = "ipg", "per";
354 #pwm-cells = <3>;
358 compatible = "fsl,imx6sl-gpt";
363 clock-names = "ipg", "per";
367 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
375 #interrupt-cells = <2>;
376 gpio-ranges = <&iomuxc 0 94 7>, <&iomuxc 7 25 25>;
380 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
385 gpio-controller;
386 #gpio-cells = <2>;
387 interrupt-controller;
388 #interrupt-cells = <2>;
389 gpio-ranges = <&iomuxc 0 50 32>;
393 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 gpio-ranges = <&iomuxc 0 82 12>, <&iomuxc 12 103 4>,
408 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
413 gpio-controller;
414 #gpio-cells = <2>;
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 gpio-ranges = <&iomuxc 0 17 8>, <&iomuxc 8 107 8>,
429 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
434 gpio-controller;
435 #gpio-cells = <2>;
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 gpio-ranges = <&iomuxc 0 135 1>, <&iomuxc 1 128 1>,
452 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
464 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
472 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
479 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
486 clks: clock-controller@20c4000 {
487 compatible = "fsl,imx6sll-ccm";
491 #clock-cells = <1>;
493 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
495 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
496 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
500 compatible = "fsl,imx6sll-anatop",
501 "fsl,imx6q-anatop",
502 "syscon", "simple-mfd";
507 #address-cells = <1>;
508 #size-cells = <0>;
510 reg_3p0: regulator-3p0@20c8120 {
511 compatible = "fsl,anatop-regulator";
513 regulator-name = "vdd3p0";
514 regulator-min-microvolt = <2625000>;
515 regulator-max-microvolt = <3400000>;
516 anatop-reg-offset = <0x120>;
517 anatop-vol-bit-shift = <8>;
518 anatop-vol-bit-width = <5>;
519 anatop-min-bit-val = <0>;
520 anatop-min-voltage = <2625000>;
521 anatop-max-voltage = <3400000>;
522 anatop-enable-bit = <0>;
525 tempmon: temperature-sensor {
526 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
528 interrupt-parent = <&gpc>;
530 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
531 nvmem-cell-names = "calib", "temp_grade";
536 usbphy1: usb-phy@20c9000 {
537 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
538 "fsl,imx23-usbphy";
542 phy-3p0-supply = <®_3p0>;
546 usbphy2: usb-phy@20ca000 {
547 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
548 "fsl,imx23-usbphy";
552 phy-reg_3p0-supply = <®_3p0>;
557 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
560 snvs_rtc: snvs-rtc-lp {
561 compatible = "fsl,sec-v4.0-mon-rtc-lp";
568 snvs_poweroff: snvs-poweroff {
569 compatible = "syscon-poweroff";
576 snvs_pwrkey: snvs-powerkey {
577 compatible = "fsl,sec-v4.0-pwrkey";
581 wakeup-source;
586 src: reset-controller@20d8000 {
587 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
591 #reset-cells = <1>;
594 gpc: interrupt-controller@20dc000 { label
595 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
597 interrupt-controller;
598 #interrupt-cells = <3>;
600 interrupt-parent = <&intc>;
604 compatible = "fsl,imx6sll-iomuxc";
608 gpr: iomuxc-gpr@20e4000 {
609 compatible = "fsl,imx6sll-iomuxc-gpr",
610 "fsl,imx6q-iomuxc-gpr", "syscon";
615 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
621 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
625 sdma: dma-controller@20ec000 {
626 compatible = "fsl,imx6sll-sdma", "fsl,imx6ul-sdma";
631 clock-names = "ipg", "ahb";
632 #dma-cells = <3>;
634 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
638 compatible = "fsl,imx6sll-pxp", "fsl,imx6ull-pxp";
643 clock-names = "axi";
646 lcdif: lcd-controller@20f8000 {
647 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
653 clock-names = "pix", "axi", "disp_axi";
658 compatible = "fsl,imx28-dcp";
664 clock-names = "dcp";
669 compatible = "fsl,aips-bus", "simple-bus";
670 #address-cells = <1>;
671 #size-cells = <1>;
676 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
677 "fsl,imx27-usb";
684 ahb-burst-config = <0x0>;
685 tx-burst-size-dword = <0x10>;
686 rx-burst-size-dword = <0x10>;
691 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
692 "fsl,imx27-usb";
698 ahb-burst-config = <0x0>;
699 tx-burst-size-dword = <0x10>;
700 rx-burst-size-dword = <0x10>;
705 #index-cells = <1>;
706 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
707 "fsl,imx6q-usbmisc";
712 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
718 clock-names = "ipg", "ahb", "per";
719 bus-width = <4>;
720 fsl,tuning-step = <2>;
721 fsl,tuning-start-tap = <20>;
726 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
732 clock-names = "ipg", "ahb", "per";
733 bus-width = <4>;
734 fsl,tuning-step = <2>;
735 fsl,tuning-start-tap = <20>;
740 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
746 clock-names = "ipg", "ahb", "per";
747 bus-width = <4>;
748 fsl,tuning-step = <2>;
749 fsl,tuning-start-tap = <20>;
754 #address-cells = <1>;
755 #size-cells = <0>;
756 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
783 mmdc: memory-controller@21b0000 {
784 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
790 compatible = "fsl,imx6sll-rngb", "fsl,imx25-rngb";
797 #address-cells = <1>;
798 #size-cells = <1>;
799 compatible = "fsl,imx6sll-ocotp", "syscon";
803 cpu_speed_grade: speed-grade@10 {
811 tempmon_temp_grade: temp-grade@20 {
817 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
823 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart",
824 "fsl,imx21-uart";
828 dma-names = "rx", "tx";
831 clock-names = "ipg", "per";