Lines Matching full:clks
68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
159 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
160 <&clks IMX6SLL_CLK_OSC>,
161 <&clks IMX6SLL_CLK_SPDIF>,
162 <&clks IMX6SLL_CLK_DUMMY>,
163 <&clks IMX6SLL_CLK_DUMMY>,
164 <&clks IMX6SLL_CLK_DUMMY>,
165 <&clks IMX6SLL_CLK_IPG>,
166 <&clks IMX6SLL_CLK_DUMMY>,
167 <&clks IMX6SLL_CLK_DUMMY>,
168 <&clks IMX6SLL_CLK_SPBA>;
183 clocks = <&clks IMX6SLL_CLK_ECSPI1>,
184 <&clks IMX6SLL_CLK_ECSPI1>;
195 clocks = <&clks IMX6SLL_CLK_ECSPI2>,
196 <&clks IMX6SLL_CLK_ECSPI2>;
207 clocks = <&clks IMX6SLL_CLK_ECSPI3>,
208 <&clks IMX6SLL_CLK_ECSPI3>;
219 clocks = <&clks IMX6SLL_CLK_ECSPI4>,
220 <&clks IMX6SLL_CLK_ECSPI4>;
232 clocks = <&clks IMX6SLL_CLK_UART4_IPG>,
233 <&clks IMX6SLL_CLK_UART4_SERIAL>;
245 clocks = <&clks IMX6SLL_CLK_UART1_IPG>,
246 <&clks IMX6SLL_CLK_UART1_SERIAL>;
258 clocks = <&clks IMX6SLL_CLK_UART2_IPG>,
259 <&clks IMX6SLL_CLK_UART2_SERIAL>;
271 clocks = <&clks IMX6SLL_CLK_SSI1_IPG>,
272 <&clks IMX6SLL_CLK_SSI1>;
284 clocks = <&clks IMX6SLL_CLK_SSI2_IPG>,
285 <&clks IMX6SLL_CLK_SSI2>;
297 clocks = <&clks IMX6SLL_CLK_SSI3_IPG>,
298 <&clks IMX6SLL_CLK_SSI3>;
310 clocks = <&clks IMX6SLL_CLK_UART3_IPG>,
311 <&clks IMX6SLL_CLK_UART3_SERIAL>;
321 clocks = <&clks IMX6SLL_CLK_PWM1>,
322 <&clks IMX6SLL_CLK_PWM1>;
331 clocks = <&clks IMX6SLL_CLK_PWM2>,
332 <&clks IMX6SLL_CLK_PWM2>;
341 clocks = <&clks IMX6SLL_CLK_PWM3>,
342 <&clks IMX6SLL_CLK_PWM3>;
351 clocks = <&clks IMX6SLL_CLK_PWM4>,
352 <&clks IMX6SLL_CLK_PWM4>;
361 clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
362 <&clks IMX6SLL_CLK_GPT_SERIAL>;
371 clocks = <&clks IMX6SLL_CLK_GPIO1>;
384 clocks = <&clks IMX6SLL_CLK_GPIO2>;
397 clocks = <&clks IMX6SLL_CLK_GPIO3>;
412 clocks = <&clks IMX6SLL_CLK_GPIO4>;
433 clocks = <&clks IMX6SLL_CLK_GPIO5>;
456 clocks = <&clks IMX6SLL_CLK_GPIO6>;
467 clocks = <&clks IMX6SLL_CLK_KPP>;
475 clocks = <&clks IMX6SLL_CLK_WDOG1>;
482 clocks = <&clks IMX6SLL_CLK_WDOG2>;
486 clks: clock-controller@20c4000 { label
495 assigned-clocks = <&clks IMX6SLL_CLK_PERCLK_SEL>;
496 assigned-clock-parents = <&clks IMX6SLL_CLK_OSC>;
532 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
541 clocks = <&clks IMX6SLL_CLK_USBPHY1>;
551 clocks = <&clks IMX6SLL_CLK_USBPHY2>;
618 clocks = <&clks IMX6SLL_CLK_DUMMY>,
619 <&clks IMX6SLL_CLK_CSI>,
620 <&clks IMX6SLL_CLK_DUMMY>;
629 clocks = <&clks IMX6SLL_CLK_IPG>,
630 <&clks IMX6SLL_CLK_SDMA>;
642 clocks = <&clks IMX6SLL_CLK_PXP>;
650 clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
651 <&clks IMX6SLL_CLK_LCDIF_APB>,
652 <&clks IMX6SLL_CLK_DUMMY>;
663 clocks = <&clks IMX6SLL_CLK_DCP>;
680 clocks = <&clks IMX6SLL_CLK_USBOH3>;
695 clocks = <&clks IMX6SLL_CLK_USBOH3>;
715 clocks = <&clks IMX6SLL_CLK_USDHC1>,
716 <&clks IMX6SLL_CLK_USDHC1>,
717 <&clks IMX6SLL_CLK_USDHC1>;
729 clocks = <&clks IMX6SLL_CLK_USDHC2>,
730 <&clks IMX6SLL_CLK_USDHC2>,
731 <&clks IMX6SLL_CLK_USDHC2>;
743 clocks = <&clks IMX6SLL_CLK_USDHC3>,
744 <&clks IMX6SLL_CLK_USDHC3>,
745 <&clks IMX6SLL_CLK_USDHC3>;
759 clocks = <&clks IMX6SLL_CLK_I2C1>;
769 clocks = <&clks IMX6SLL_CLK_I2C2>;
779 clocks = <&clks IMX6SLL_CLK_I2C3>;
786 clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;
793 clocks = <&clks IMX6SLL_CLK_DUMMY>;
801 clocks = <&clks IMX6SLL_CLK_OCOTP>;
829 clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
830 <&clks IMX6SLL_CLK_UART5_SERIAL>;