Lines Matching +full:regulator +full:- +full:microvolt +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6sl-pinfunc.h"
7 #include <dt-bindings/clock/imx6sl-clock.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a9";
54 next-level-cache = <&L2>;
55 operating-points = <
61 fsl,soc-operating-points = <
62 /* ARM kHz SOC-PU uV */
67 clock-latency = <61036>; /* two CLK32 periods */
68 #cooling-cells = <2>;
72 clock-names = "arm", "pll2_pfd2_396m", "step",
74 arm-supply = <®_arm>;
75 pu-supply = <®_pu>;
76 soc-supply = <®_soc>;
77 nvmem-cells = <&cpu_speed_grade>;
78 nvmem-cell-names = "speed_grade";
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <32768>;
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <24000000>;
97 compatible = "arm,cortex-a9-pmu";
98 interrupt-parent = <&gpc>;
103 compatible = "usb-nop-xceiv";
104 #phy-cells = <0>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "simple-bus";
111 interrupt-parent = <&gpc>;
115 compatible = "mmio-sram";
120 intc: interrupt-controller@a01000 {
121 compatible = "arm,cortex-a9-gic";
122 #interrupt-cells = <3>;
123 interrupt-controller;
126 interrupt-parent = <&intc>;
129 L2: cache-controller@a02000 {
130 compatible = "arm,pl310-cache";
133 cache-unified;
134 cache-level = <2>;
135 arm,tag-latency = <4 2 3>;
136 arm,data-latency = <4 2 3>;
140 compatible = "fsl,aips-bus", "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
146 spba: spba-bus@2000000 {
147 compatible = "fsl,spba-bus", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
154 compatible = "fsl,imx6sl-spdif",
155 "fsl,imx35-spdif";
160 dma-names = "rx", "tx";
166 clock-names = "core", "rxtx0",
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
182 clock-names = "ipg", "per";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
194 clock-names = "ipg", "per";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
206 clock-names = "ipg", "per";
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
218 clock-names = "ipg", "per";
223 compatible = "fsl,imx6sl-uart",
224 "fsl,imx6q-uart", "fsl,imx21-uart";
229 clock-names = "ipg", "per";
231 dma-names = "rx", "tx";
236 compatible = "fsl,imx6sl-uart",
237 "fsl,imx6q-uart", "fsl,imx21-uart";
242 clock-names = "ipg", "per";
244 dma-names = "rx", "tx";
249 compatible = "fsl,imx6sl-uart",
250 "fsl,imx6q-uart", "fsl,imx21-uart";
255 clock-names = "ipg", "per";
257 dma-names = "rx", "tx";
262 #sound-dai-cells = <0>;
263 compatible = "fsl,imx6sl-ssi",
264 "fsl,imx51-ssi";
269 clock-names = "ipg", "baud";
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6sl-ssi",
280 "fsl,imx51-ssi";
285 clock-names = "ipg", "baud";
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
294 #sound-dai-cells = <0>;
295 compatible = "fsl,imx6sl-ssi",
296 "fsl,imx51-ssi";
301 clock-names = "ipg", "baud";
304 dma-names = "rx", "tx";
305 fsl,fifo-depth = <15>;
310 compatible = "fsl,imx6sl-uart",
311 "fsl,imx6q-uart", "fsl,imx21-uart";
316 clock-names = "ipg", "per";
318 dma-names = "rx", "tx";
323 compatible = "fsl,imx6sl-uart",
324 "fsl,imx6q-uart", "fsl,imx21-uart";
329 clock-names = "ipg", "per";
331 dma-names = "rx", "tx";
337 #pwm-cells = <3>;
338 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
343 clock-names = "ipg", "per";
347 #pwm-cells = <3>;
348 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
353 clock-names = "ipg", "per";
357 #pwm-cells = <3>;
358 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
363 clock-names = "ipg", "per";
367 #pwm-cells = <3>;
368 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
373 clock-names = "ipg", "per";
377 compatible = "fsl,imx6sl-gpt";
382 clock-names = "ipg", "per";
386 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
403 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
421 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
440 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
466 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
488 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
496 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
503 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
510 clks: clock-controller@20c4000 {
511 compatible = "fsl,imx6sl-ccm";
515 #clock-cells = <1>;
519 compatible = "fsl,imx6sl-anatop",
520 "fsl,imx6q-anatop",
521 "syscon", "simple-mfd";
527 reg_vdd1p1: regulator-1p1 {
528 compatible = "fsl,anatop-regulator";
529 regulator-name = "vdd1p1";
530 regulator-min-microvolt = <1000000>;
531 regulator-max-microvolt = <1200000>;
532 regulator-always-on;
533 anatop-reg-offset = <0x110>;
534 anatop-vol-bit-shift = <8>;
535 anatop-vol-bit-width = <5>;
536 anatop-min-bit-val = <4>;
537 anatop-min-voltage = <800000>;
538 anatop-max-voltage = <1375000>;
539 anatop-enable-bit = <0>;
542 reg_vdd3p0: regulator-3p0 {
543 compatible = "fsl,anatop-regulator";
544 regulator-name = "vdd3p0";
545 regulator-min-microvolt = <2800000>;
546 regulator-max-microvolt = <3150000>;
547 regulator-always-on;
548 anatop-reg-offset = <0x120>;
549 anatop-vol-bit-shift = <8>;
550 anatop-vol-bit-width = <5>;
551 anatop-min-bit-val = <0>;
552 anatop-min-voltage = <2625000>;
553 anatop-max-voltage = <3400000>;
554 anatop-enable-bit = <0>;
557 reg_vdd2p5: regulator-2p5 {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd2p5";
560 regulator-min-microvolt = <2250000>;
561 regulator-max-microvolt = <2750000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x130>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2100000>;
568 anatop-max-voltage = <2850000>;
569 anatop-enable-bit = <0>;
572 reg_arm: regulator-vddcore {
573 compatible = "fsl,anatop-regulator";
574 regulator-name = "vddarm";
575 regulator-min-microvolt = <725000>;
576 regulator-max-microvolt = <1450000>;
577 regulator-always-on;
578 anatop-reg-offset = <0x140>;
579 anatop-vol-bit-shift = <0>;
580 anatop-vol-bit-width = <5>;
581 anatop-delay-reg-offset = <0x170>;
582 anatop-delay-bit-shift = <24>;
583 anatop-delay-bit-width = <2>;
584 anatop-min-bit-val = <1>;
585 anatop-min-voltage = <725000>;
586 anatop-max-voltage = <1450000>;
589 reg_pu: regulator-vddpu {
590 compatible = "fsl,anatop-regulator";
591 regulator-name = "vddpu";
592 regulator-min-microvolt = <725000>;
593 regulator-max-microvolt = <1450000>;
594 anatop-reg-offset = <0x140>;
595 anatop-vol-bit-shift = <9>;
596 anatop-vol-bit-width = <5>;
597 anatop-delay-reg-offset = <0x170>;
598 anatop-delay-bit-shift = <26>;
599 anatop-delay-bit-width = <2>;
600 anatop-min-bit-val = <1>;
601 anatop-min-voltage = <725000>;
602 anatop-max-voltage = <1450000>;
605 reg_soc: regulator-vddsoc {
606 compatible = "fsl,anatop-regulator";
607 regulator-name = "vddsoc";
608 regulator-min-microvolt = <725000>;
609 regulator-max-microvolt = <1450000>;
610 regulator-always-on;
611 anatop-reg-offset = <0x140>;
612 anatop-vol-bit-shift = <18>;
613 anatop-vol-bit-width = <5>;
614 anatop-delay-reg-offset = <0x170>;
615 anatop-delay-bit-shift = <28>;
616 anatop-delay-bit-width = <2>;
617 anatop-min-bit-val = <1>;
618 anatop-min-voltage = <725000>;
619 anatop-max-voltage = <1450000>;
623 compatible = "fsl,imx6q-tempmon";
625 interrupt-parent = <&gpc>;
627 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
628 nvmem-cell-names = "calib", "temp_grade";
634 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
642 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
650 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
653 snvs_rtc: snvs-rtc-lp {
654 compatible = "fsl,sec-v4.0-mon-rtc-lp";
656 offset = <0x34>;
661 snvs_poweroff: snvs-poweroff {
662 compatible = "syscon-poweroff";
664 offset = <0x38>;
681 src: reset-controller@20d8000 {
682 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
686 #reset-cells = <1>;
690 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
692 interrupt-controller;
693 #interrupt-cells = <3>;
695 interrupt-parent = <&intc>;
697 clock-names = "ipg";
700 #address-cells = <1>;
701 #size-cells = <0>;
703 power-domain@0 {
705 #power-domain-cells = <0>;
708 pd_pu: power-domain@1 {
710 #power-domain-cells = <0>;
711 power-supply = <®_pu>;
716 pd_disp: power-domain@2 {
718 #power-domain-cells = <0>;
728 gpr: iomuxc-gpr@20e0000 {
729 compatible = "fsl,imx6sl-iomuxc-gpr",
730 "fsl,imx6q-iomuxc-gpr", "syscon";
735 compatible = "fsl,imx6sl-iomuxc";
750 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
755 clock-names = "ipg", "ahb";
756 #dma-cells = <3>;
758 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
772 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
778 clock-names = "pix", "axi", "disp_axi";
780 power-domains = <&pd_disp>;
784 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
793 compatible = "fsl,aips-bus", "simple-bus";
794 #address-cells = <1>;
795 #size-cells = <1>;
800 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
806 ahb-burst-config = <0x0>;
807 tx-burst-size-dword = <0x10>;
808 rx-burst-size-dword = <0x10>;
813 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
819 ahb-burst-config = <0x0>;
820 tx-burst-size-dword = <0x10>;
821 rx-burst-size-dword = <0x10>;
826 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
834 ahb-burst-config = <0x0>;
835 tx-burst-size-dword = <0x10>;
836 rx-burst-size-dword = <0x10>;
841 #index-cells = <1>;
842 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
853 clock-names = "ipg", "ahb";
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
864 clock-names = "ipg", "ahb", "per";
865 bus-width = <4>;
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
876 clock-names = "ipg", "ahb", "per";
877 bus-width = <4>;
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
888 clock-names = "ipg", "ahb", "per";
889 bus-width = <4>;
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
900 clock-names = "ipg", "ahb", "per";
901 bus-width = <4>;
906 #address-cells = <1>;
907 #size-cells = <0>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
916 #address-cells = <1>;
917 #size-cells = <0>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
926 #address-cells = <1>;
927 #size-cells = <0>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
935 memory-controller@21b0000 {
936 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
942 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb";
949 #address-cells = <2>;
950 #size-cells = <1>;
953 fsl,weim-cs-gpr = <&gpr>;
958 compatible = "fsl,imx6sl-ocotp", "syscon";
961 #address-cells = <1>;
962 #size-cells = <1>;
964 cpu_speed_grade: speed-grade@10 {
972 tempmon_temp_grade: temp-grade@20 {
978 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
990 clock-names = "bus", "core";
991 power-domains = <&pd_pu>;
1000 clock-names = "bus", "core";
1001 power-domains = <&pd_pu>;