Lines Matching +full:imx51 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
54 compatible = "fsl,imx-ckil", "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <32768>;
60 compatible = "fsl,imx-ckih1", "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <0>;
66 compatible = "fsl,imx-osc", "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <24000000>;
73 #address-cells = <1>;
74 #size-cells = <0>;
75 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
79 lvds-channel@0 {
80 #address-cells = <1>;
81 #size-cells = <0>;
89 remote-endpoint = <&ipu1_di0_lvds0>;
97 remote-endpoint = <&ipu1_di1_lvds0>;
102 lvds-channel@1 {
103 #address-cells = <1>;
104 #size-cells = <0>;
112 remote-endpoint = <&ipu1_di0_lvds1>;
120 remote-endpoint = <&ipu1_di1_lvds1>;
127 compatible = "arm,cortex-a9-pmu";
128 interrupt-parent = <&gpc>;
133 compatible = "usb-nop-xceiv";
134 #phy-cells = <0>;
138 compatible = "usb-nop-xceiv";
139 #phy-cells = <0>;
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "simple-bus";
146 interrupt-parent = <&gpc>;
149 dma_apbh: dma-apbh@110000 {
150 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
156 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
157 #dma-cells = <1>;
158 dma-channels = <4>;
162 gpmi: nand-controller@112000 {
163 compatible = "fsl,imx6q-gpmi-nand";
165 reg-names = "gpmi-nand", "bch";
167 interrupt-names = "bch";
173 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
176 dma-names = "rx-tx";
181 #address-cells = <1>;
182 #size-cells = <0>;
188 clock-names = "iahb", "isfr";
195 remote-endpoint = <&ipu1_di0_hdmi>;
203 remote-endpoint = <&ipu1_di1_hdmi>;
215 clock-names = "bus", "core", "shader";
216 power-domains = <&pd_pu>;
217 #cooling-cells = <2>;
226 clock-names = "bus", "core";
227 power-domains = <&pd_pu>;
228 #cooling-cells = <2>;
232 compatible = "arm,cortex-a9-twd-timer";
235 interrupt-parent = <&intc>;
239 intc: interrupt-controller@a01000 {
240 compatible = "arm,cortex-a9-gic";
241 #interrupt-cells = <3>;
242 interrupt-controller;
245 interrupt-parent = <&intc>;
248 L2: cache-controller@a02000 {
249 compatible = "arm,pl310-cache";
252 cache-unified;
253 cache-level = <2>;
254 arm,tag-latency = <4 2 3>;
255 arm,data-latency = <4 2 3>;
256 arm,shared-override;
260 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
263 reg-names = "dbi", "config";
264 #address-cells = <3>;
265 #size-cells = <2>;
267 bus-range = <0x00 0xff>;
269 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
270 num-lanes = <1>;
271 num-viewport = <4>;
273 interrupt-names = "msi";
274 #interrupt-cells = <1>;
275 interrupt-map-mask = <0 0 0 0x7>;
276 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
283 clock-names = "pcie", "pcie_bus", "pcie_phy";
288 compatible = "fsl,aips-bus", "simple-bus";
289 #address-cells = <1>;
290 #size-cells = <1>;
294 spba-bus@2000000 {
295 compatible = "fsl,spba-bus", "simple-bus";
296 #address-cells = <1>;
297 #size-cells = <1>;
302 compatible = "fsl,imx35-spdif";
307 dma-names = "rx", "tx";
313 clock-names = "core", "rxtx0",
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
329 clock-names = "ipg", "per";
331 dma-names = "rx", "tx";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
343 clock-names = "ipg", "per";
345 dma-names = "rx", "tx";
350 #address-cells = <1>;
351 #size-cells = <0>;
352 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
357 clock-names = "ipg", "per";
359 dma-names = "rx", "tx";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
371 clock-names = "ipg", "per";
373 dma-names = "rx", "tx";
378 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
383 clock-names = "ipg", "per";
385 dma-names = "rx", "tx";
390 #sound-dai-cells = <0>;
391 compatible = "fsl,imx35-esai";
399 clock-names = "core", "mem", "extal", "fsys", "spba";
401 dma-names = "rx", "tx";
406 #sound-dai-cells = <0>;
407 compatible = "fsl,imx6q-ssi",
408 "fsl,imx51-ssi";
413 clock-names = "ipg", "baud";
416 dma-names = "rx", "tx";
417 fsl,fifo-depth = <15>;
422 #sound-dai-cells = <0>;
423 compatible = "fsl,imx6q-ssi",
424 "fsl,imx51-ssi";
429 clock-names = "ipg", "baud";
432 dma-names = "rx", "tx";
433 fsl,fifo-depth = <15>;
438 #sound-dai-cells = <0>;
439 compatible = "fsl,imx6q-ssi",
440 "fsl,imx51-ssi";
445 clock-names = "ipg", "baud";
448 dma-names = "rx", "tx";
449 fsl,fifo-depth = <15>;
454 compatible = "fsl,imx53-asrc";
464 clock-names = "mem", "ipg", "asrck_0",
471 dma-names = "rxa", "rxb", "rxc",
473 fsl,asrc-rate = <48000>;
474 fsl,asrc-width = <16>;
488 interrupt-names = "bit", "jpeg";
491 clock-names = "per", "ahb";
492 power-domains = <&pd_pu>;
502 #pwm-cells = <3>;
503 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
508 clock-names = "ipg", "per";
513 #pwm-cells = <3>;
514 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
519 clock-names = "ipg", "per";
524 #pwm-cells = <3>;
525 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
530 clock-names = "ipg", "per";
535 #pwm-cells = <3>;
536 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
541 clock-names = "ipg", "per";
546 compatible = "fsl,imx6q-flexcan";
551 clock-names = "ipg", "per";
552 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
557 compatible = "fsl,imx6q-flexcan";
562 clock-names = "ipg", "per";
563 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
568 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
574 clock-names = "ipg", "per", "osc_per";
578 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
589 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
593 gpio-controller;
594 #gpio-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <2>;
600 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
604 gpio-controller;
605 #gpio-cells = <2>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
611 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
615 gpio-controller;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
622 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
626 gpio-controller;
627 #gpio-cells = <2>;
628 interrupt-controller;
629 #interrupt-cells = <2>;
633 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
637 gpio-controller;
638 #gpio-cells = <2>;
639 interrupt-controller;
640 #interrupt-cells = <2>;
644 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
648 gpio-controller;
649 #gpio-cells = <2>;
650 interrupt-controller;
651 #interrupt-cells = <2>;
655 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
663 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
670 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
677 clks: clock-controller@20c4000 {
678 compatible = "fsl,imx6q-ccm";
682 #clock-cells = <1>;
686 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
692 reg_vdd1p1: regulator-1p1 {
693 compatible = "fsl,anatop-regulator";
694 regulator-name = "vdd1p1";
695 regulator-min-microvolt = <1000000>;
696 regulator-max-microvolt = <1200000>;
697 regulator-always-on;
698 anatop-reg-offset = <0x110>;
699 anatop-vol-bit-shift = <8>;
700 anatop-vol-bit-width = <5>;
701 anatop-min-bit-val = <4>;
702 anatop-min-voltage = <800000>;
703 anatop-max-voltage = <1375000>;
704 anatop-enable-bit = <0>;
707 reg_vdd3p0: regulator-3p0 {
708 compatible = "fsl,anatop-regulator";
709 regulator-name = "vdd3p0";
710 regulator-min-microvolt = <2800000>;
711 regulator-max-microvolt = <3150000>;
712 regulator-always-on;
713 anatop-reg-offset = <0x120>;
714 anatop-vol-bit-shift = <8>;
715 anatop-vol-bit-width = <5>;
716 anatop-min-bit-val = <0>;
717 anatop-min-voltage = <2625000>;
718 anatop-max-voltage = <3400000>;
719 anatop-enable-bit = <0>;
722 reg_vdd2p5: regulator-2p5 {
723 compatible = "fsl,anatop-regulator";
724 regulator-name = "vdd2p5";
725 regulator-min-microvolt = <2250000>;
726 regulator-max-microvolt = <2750000>;
727 regulator-always-on;
728 anatop-reg-offset = <0x130>;
729 anatop-vol-bit-shift = <8>;
730 anatop-vol-bit-width = <5>;
731 anatop-min-bit-val = <0>;
732 anatop-min-voltage = <2100000>;
733 anatop-max-voltage = <2875000>;
734 anatop-enable-bit = <0>;
737 reg_arm: regulator-vddcore {
738 compatible = "fsl,anatop-regulator";
739 regulator-name = "vddarm";
740 regulator-min-microvolt = <725000>;
741 regulator-max-microvolt = <1450000>;
742 regulator-always-on;
743 anatop-reg-offset = <0x140>;
744 anatop-vol-bit-shift = <0>;
745 anatop-vol-bit-width = <5>;
746 anatop-delay-reg-offset = <0x170>;
747 anatop-delay-bit-shift = <24>;
748 anatop-delay-bit-width = <2>;
749 anatop-min-bit-val = <1>;
750 anatop-min-voltage = <725000>;
751 anatop-max-voltage = <1450000>;
754 reg_pu: regulator-vddpu {
755 compatible = "fsl,anatop-regulator";
756 regulator-name = "vddpu";
757 regulator-min-microvolt = <725000>;
758 regulator-max-microvolt = <1450000>;
759 regulator-enable-ramp-delay = <150>;
760 anatop-reg-offset = <0x140>;
761 anatop-vol-bit-shift = <9>;
762 anatop-vol-bit-width = <5>;
763 anatop-delay-reg-offset = <0x170>;
764 anatop-delay-bit-shift = <26>;
765 anatop-delay-bit-width = <2>;
766 anatop-min-bit-val = <1>;
767 anatop-min-voltage = <725000>;
768 anatop-max-voltage = <1450000>;
771 reg_soc: regulator-vddsoc {
772 compatible = "fsl,anatop-regulator";
773 regulator-name = "vddsoc";
774 regulator-min-microvolt = <725000>;
775 regulator-max-microvolt = <1450000>;
776 regulator-always-on;
777 anatop-reg-offset = <0x140>;
778 anatop-vol-bit-shift = <18>;
779 anatop-vol-bit-width = <5>;
780 anatop-delay-reg-offset = <0x170>;
781 anatop-delay-bit-shift = <28>;
782 anatop-delay-bit-width = <2>;
783 anatop-min-bit-val = <1>;
784 anatop-min-voltage = <725000>;
785 anatop-max-voltage = <1450000>;
789 compatible = "fsl,imx6q-tempmon";
790 interrupt-parent = <&gpc>;
793 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
794 nvmem-cell-names = "calib", "temp_grade";
796 #thermal-sensor-cells = <0>;
801 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
809 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
817 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
820 snvs_rtc: snvs-rtc-lp {
821 compatible = "fsl,sec-v4.0-mon-rtc-lp";
828 snvs_poweroff: snvs-poweroff {
829 compatible = "syscon-poweroff";
837 snvs_pwrkey: snvs-powerkey {
838 compatible = "fsl,sec-v4.0-pwrkey";
842 wakeup-source;
846 snvs_lpgpr: snvs-lpgpr {
847 compatible = "fsl,imx6q-snvs-lpgpr";
861 src: reset-controller@20d8000 {
862 compatible = "fsl,imx6q-src", "fsl,imx51-src";
866 #reset-cells = <1>;
870 compatible = "fsl,imx6q-gpc";
872 interrupt-controller;
873 #interrupt-cells = <3>;
875 interrupt-parent = <&intc>;
877 clock-names = "ipg";
880 #address-cells = <1>;
881 #size-cells = <0>;
883 power-domain@0 {
885 #power-domain-cells = <0>;
887 pd_pu: power-domain@1 {
889 #power-domain-cells = <0>;
890 power-supply = <®_pu>;
901 gpr: iomuxc-gpr@20e0000 {
902 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
905 mux: mux-controller {
906 compatible = "mmio-mux";
907 #mux-control-cells = <1>;
912 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
927 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
932 clock-names = "ipg", "ahb";
933 #dma-cells = <3>;
934 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
939 compatible = "fsl,aips-bus", "simple-bus";
940 #address-cells = <1>;
941 #size-cells = <1>;
946 compatible = "fsl,sec-v4.0";
947 #address-cells = <1>;
948 #size-cells = <1>;
955 clock-names = "mem", "aclk", "ipg", "emi_slow";
958 compatible = "fsl,sec-v4.0-job-ring";
964 compatible = "fsl,sec-v4.0-job-ring";
975 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
981 ahb-burst-config = <0x0>;
982 tx-burst-size-dword = <0x10>;
983 rx-burst-size-dword = <0x10>;
988 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
995 ahb-burst-config = <0x0>;
996 tx-burst-size-dword = <0x10>;
997 rx-burst-size-dword = <0x10>;
1002 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1010 ahb-burst-config = <0x0>;
1011 tx-burst-size-dword = <0x10>;
1012 rx-burst-size-dword = <0x10>;
1017 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1025 ahb-burst-config = <0x0>;
1026 tx-burst-size-dword = <0x10>;
1027 rx-burst-size-dword = <0x10>;
1032 #index-cells = <1>;
1033 compatible = "fsl,imx6q-usbmisc";
1039 compatible = "fsl,imx6q-fec";
1041 interrupt-names = "int0", "pps";
1048 clock-names = "ipg", "ahb", "ptp", "enet_out";
1049 fsl,stop-mode = <&gpr 0x34 27>;
1061 compatible = "fsl,imx6q-usdhc";
1067 clock-names = "ipg", "ahb", "per";
1068 bus-width = <4>;
1073 compatible = "fsl,imx6q-usdhc";
1079 clock-names = "ipg", "ahb", "per";
1080 bus-width = <4>;
1085 compatible = "fsl,imx6q-usdhc";
1091 clock-names = "ipg", "ahb", "per";
1092 bus-width = <4>;
1097 compatible = "fsl,imx6q-usdhc";
1103 clock-names = "ipg", "ahb", "per";
1104 bus-width = <4>;
1108 i2c1: i2c@21a0000 {
1109 #address-cells = <1>;
1110 #size-cells = <0>;
1111 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1118 i2c2: i2c@21a4000 {
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1128 i2c3: i2c@21a8000 {
1129 #address-cells = <1>;
1130 #size-cells = <0>;
1131 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1142 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1143 compatible = "fsl,imx6q-mmdc";
1148 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1149 compatible = "fsl,imx6q-mmdc";
1155 #address-cells = <2>;
1156 #size-cells = <1>;
1157 compatible = "fsl,imx6q-weim";
1161 fsl,weim-cs-gpr = <&gpr>;
1166 compatible = "fsl,imx6q-ocotp", "syscon";
1169 #address-cells = <1>;
1170 #size-cells = <1>;
1172 cpu_speed_grade: speed-grade@10 {
1180 tempmon_temp_grade: temp-grade@20 {
1196 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1202 compatible = "fsl,imx6-mipi-csi2";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1210 clock-names = "dphy", "ref", "pix";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1226 remote-endpoint = <&ipu1_di0_mipi>;
1234 remote-endpoint = <&ipu1_di1_mipi>;
1241 compatible = "fsl,imx6q-vdoa";
1248 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1253 clock-names = "ipg", "per";
1255 dma-names = "rx", "tx";
1260 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1265 clock-names = "ipg", "per";
1267 dma-names = "rx", "tx";
1272 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1277 clock-names = "ipg", "per";
1279 dma-names = "rx", "tx";
1284 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1289 clock-names = "ipg", "per";
1291 dma-names = "rx", "tx";
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1299 compatible = "fsl,imx6q-ipu";
1306 clock-names = "bus", "di0", "di1";
1313 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1332 remote-endpoint = <&hdmi_mux_0>;
1337 remote-endpoint = <&mipi_mux_0>;
1342 remote-endpoint = <&lvds0_mux_0>;
1347 remote-endpoint = <&lvds1_mux_0>;
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1362 remote-endpoint = <&hdmi_mux_1>;
1367 remote-endpoint = <&mipi_mux_1>;
1372 remote-endpoint = <&lvds0_mux_1>;
1377 remote-endpoint = <&lvds1_mux_1>;