Lines Matching +full:0 +full:x020c4000
55 #clock-cells = <0>;
61 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
74 #size-cells = <0>;
79 lvds-channel@0 {
81 #size-cells = <0>;
82 reg = <0>;
85 port@0 {
86 reg = <0>;
104 #size-cells = <0>;
108 port@0 {
109 reg = <0>;
129 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
134 #phy-cells = <0>;
139 #phy-cells = <0>;
151 reg = <0x00110000 0x2000>;
152 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
153 <0 13 IRQ_TYPE_LEVEL_HIGH>,
154 <0 13 IRQ_TYPE_LEVEL_HIGH>,
155 <0 13 IRQ_TYPE_LEVEL_HIGH>;
164 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
166 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
175 dmas = <&dma_apbh 0>;
182 #size-cells = <0>;
183 reg = <0x00120000 0x9000>;
184 interrupts = <0 115 0x04>;
191 port@0 {
192 reg = <0>;
210 reg = <0x00130000 0x4000>;
211 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
222 reg = <0x00134000 0x4000>;
223 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
233 reg = <0x00a00600 0x20>;
234 interrupts = <1 13 0xf01>;
243 reg = <0x00a01000 0x1000>,
244 <0x00a00100 0x100>;
250 reg = <0x00a02000 0x1000>;
251 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
261 reg = <0x01ffc000 0x04000>,
262 <0x01f00000 0x80000>;
267 bus-range = <0x00 0xff>;
268 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
269 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
275 interrupt-map-mask = <0 0 0 0x7>;
276 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
277 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
278 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
279 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
291 reg = <0x02000000 0x100000>;
298 reg = <0x02000000 0x40000>;
303 reg = <0x02004000 0x4000>;
304 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
305 dmas = <&sdma 14 18 0>,
306 <&sdma 15 18 0>;
323 #size-cells = <0>;
325 reg = <0x02008000 0x4000>;
326 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
337 #size-cells = <0>;
339 reg = <0x0200c000 0x4000>;
340 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
351 #size-cells = <0>;
353 reg = <0x02010000 0x4000>;
354 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
365 #size-cells = <0>;
367 reg = <0x02014000 0x4000>;
368 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
379 reg = <0x02020000 0x4000>;
380 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
384 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
390 #sound-dai-cells = <0>;
392 reg = <0x02024000 0x4000>;
393 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
400 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
406 #sound-dai-cells = <0>;
409 reg = <0x02028000 0x4000>;
410 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
414 dmas = <&sdma 37 1 0>,
415 <&sdma 38 1 0>;
422 #sound-dai-cells = <0>;
425 reg = <0x0202c000 0x4000>;
426 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
430 dmas = <&sdma 41 1 0>,
431 <&sdma 42 1 0>;
438 #sound-dai-cells = <0>;
441 reg = <0x02030000 0x4000>;
442 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&sdma 45 1 0>,
447 <&sdma 46 1 0>;
455 reg = <0x02034000 0x4000>;
456 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
458 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
459 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
460 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
461 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
462 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
479 reg = <0x0203c000 0x4000>;
485 reg = <0x02040000 0x3c000>;
486 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
487 <0 3 IRQ_TYPE_LEVEL_HIGH>;
498 reg = <0x0207c000 0x4000>;
504 reg = <0x02080000 0x4000>;
505 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
515 reg = <0x02084000 0x4000>;
516 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
526 reg = <0x02088000 0x4000>;
527 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
537 reg = <0x0208c000 0x4000>;
538 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
547 reg = <0x02090000 0x4000>;
548 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
552 fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
558 reg = <0x02094000 0x4000>;
559 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
563 fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
569 reg = <0x02098000 0x4000>;
570 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
579 reg = <0x0209c000 0x4000>;
580 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
581 <0 67 IRQ_TYPE_LEVEL_HIGH>;
590 reg = <0x020a0000 0x4000>;
591 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
592 <0 69 IRQ_TYPE_LEVEL_HIGH>;
601 reg = <0x020a4000 0x4000>;
602 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
603 <0 71 IRQ_TYPE_LEVEL_HIGH>;
612 reg = <0x020a8000 0x4000>;
613 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
614 <0 73 IRQ_TYPE_LEVEL_HIGH>;
623 reg = <0x020ac000 0x4000>;
624 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
625 <0 75 IRQ_TYPE_LEVEL_HIGH>;
634 reg = <0x020b0000 0x4000>;
635 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
636 <0 77 IRQ_TYPE_LEVEL_HIGH>;
645 reg = <0x020b4000 0x4000>;
646 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
647 <0 79 IRQ_TYPE_LEVEL_HIGH>;
656 reg = <0x020b8000 0x4000>;
657 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
664 reg = <0x020bc000 0x4000>;
665 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
671 reg = <0x020c0000 0x4000>;
672 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
679 reg = <0x020c4000 0x4000>;
680 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
681 <0 88 IRQ_TYPE_LEVEL_HIGH>;
687 reg = <0x020c8000 0x1000>;
688 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
689 <0 54 IRQ_TYPE_LEVEL_HIGH>,
690 <0 127 IRQ_TYPE_LEVEL_HIGH>;
698 anatop-reg-offset = <0x110>;
704 anatop-enable-bit = <0>;
713 anatop-reg-offset = <0x120>;
716 anatop-min-bit-val = <0>;
719 anatop-enable-bit = <0>;
728 anatop-reg-offset = <0x130>;
731 anatop-min-bit-val = <0>;
734 anatop-enable-bit = <0>;
743 anatop-reg-offset = <0x140>;
744 anatop-vol-bit-shift = <0>;
746 anatop-delay-reg-offset = <0x170>;
760 anatop-reg-offset = <0x140>;
763 anatop-delay-reg-offset = <0x170>;
777 anatop-reg-offset = <0x140>;
780 anatop-delay-reg-offset = <0x170>;
791 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
796 #thermal-sensor-cells = <0>;
802 reg = <0x020c9000 0x1000>;
803 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
810 reg = <0x020ca000 0x1000>;
811 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
817 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
818 reg = <0x020cc000 0x4000>;
821 compatible = "fsl,sec-v4.0-mon-rtc-lp";
823 offset = <0x34>;
824 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
825 <0 20 IRQ_TYPE_LEVEL_HIGH>;
831 offset = <0x38>;
832 value = <0x60>;
833 mask = <0x60>;
838 compatible = "fsl,sec-v4.0-pwrkey";
852 reg = <0x020d0000 0x4000>;
853 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
857 reg = <0x020d4000 0x4000>;
858 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
863 reg = <0x020d8000 0x4000>;
864 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
865 <0 96 IRQ_TYPE_LEVEL_HIGH>;
871 reg = <0x020dc000 0x4000>;
874 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
881 #size-cells = <0>;
883 power-domain@0 {
884 reg = <0>;
885 #power-domain-cells = <0>;
889 #power-domain-cells = <0>;
903 reg = <0x20e0000 0x38>;
913 reg = <0x20e0000 0x4000>;
917 reg = <0x020e4000 0x4000>;
918 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
922 reg = <0x020e8000 0x4000>;
923 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
928 reg = <0x020ec000 0x4000>;
929 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
942 reg = <0x02100000 0x100000>;
946 compatible = "fsl,sec-v4.0";
949 reg = <0x2100000 0x10000>;
950 ranges = <0 0x2100000 0x10000>;
958 compatible = "fsl,sec-v4.0-job-ring";
959 reg = <0x1000 0x1000>;
964 compatible = "fsl,sec-v4.0-job-ring";
965 reg = <0x2000 0x1000>;
971 reg = <0x0217c000 0x4000>;
976 reg = <0x02184000 0x200>;
977 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
980 fsl,usbmisc = <&usbmisc 0>;
981 ahb-burst-config = <0x0>;
982 tx-burst-size-dword = <0x10>;
983 rx-burst-size-dword = <0x10>;
989 reg = <0x02184200 0x200>;
990 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
995 ahb-burst-config = <0x0>;
996 tx-burst-size-dword = <0x10>;
997 rx-burst-size-dword = <0x10>;
1003 reg = <0x02184400 0x200>;
1004 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1010 ahb-burst-config = <0x0>;
1011 tx-burst-size-dword = <0x10>;
1012 rx-burst-size-dword = <0x10>;
1018 reg = <0x02184600 0x200>;
1019 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1025 ahb-burst-config = <0x0>;
1026 tx-burst-size-dword = <0x10>;
1027 rx-burst-size-dword = <0x10>;
1034 reg = <0x02184800 0x200>;
1040 reg = <0x02188000 0x4000>;
1042 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
1043 <0 119 IRQ_TYPE_LEVEL_HIGH>;
1049 fsl,stop-mode = <&gpr 0x34 27>;
1054 reg = <0x0218c000 0x4000>;
1055 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1056 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1057 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1062 reg = <0x02190000 0x4000>;
1063 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1074 reg = <0x02194000 0x4000>;
1075 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1086 reg = <0x02198000 0x4000>;
1087 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1098 reg = <0x0219c000 0x4000>;
1099 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1110 #size-cells = <0>;
1112 reg = <0x021a0000 0x4000>;
1113 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1120 #size-cells = <0>;
1122 reg = <0x021a4000 0x4000>;
1123 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1130 #size-cells = <0>;
1132 reg = <0x021a8000 0x4000>;
1133 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1139 reg = <0x021ac000 0x4000>;
1144 reg = <0x021b0000 0x4000>;
1150 reg = <0x021b4000 0x4000>;
1158 reg = <0x021b8000 0x4000>;
1159 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1167 reg = <0x021bc000 0x4000>;
1173 reg = <0x10 4>;
1177 reg = <0x38 4>;
1181 reg = <0x20 4>;
1186 reg = <0x021d0000 0x4000>;
1187 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1191 reg = <0x021d4000 0x4000>;
1192 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1197 reg = <0x021d8000 0x4000>;
1203 reg = <0x021dc000 0x4000>;
1205 #size-cells = <0>;
1206 interrupts = <0 100 0x04>, <0 101 0x04>;
1215 reg = <0x021e0000 0x4000>;
1220 #size-cells = <0>;
1222 port@0 {
1223 reg = <0>;
1242 reg = <0x021e4000 0x4000>;
1243 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1249 reg = <0x021e8000 0x4000>;
1250 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1254 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1261 reg = <0x021ec000 0x4000>;
1262 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1266 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1273 reg = <0x021f0000 0x4000>;
1274 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1278 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1285 reg = <0x021f4000 0x4000>;
1286 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1290 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1298 #size-cells = <0>;
1300 reg = <0x02400000 0x400000>;
1301 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1309 ipu1_csi0: port@0 {
1310 reg = <0>;
1323 #size-cells = <0>;
1326 ipu1_di0_disp0: endpoint@0 {
1327 reg = <0>;
1353 #size-cells = <0>;
1356 ipu1_di1_disp1: endpoint@0 {
1357 reg = <0>;