Lines Matching +full:imx21 +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
35 clock-latency = <61036>; /* two CLK32 periods */
36 #cooling-cells = <2>;
42 clock-names = "arm", "pll2_pfd2_396m", "step",
44 arm-supply = <®_arm>;
45 pu-supply = <®_pu>;
46 soc-supply = <®_soc>;
47 nvmem-cells = <&cpu_speed_grade>;
48 nvmem-cell-names = "speed_grade";
52 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
56 operating-points = <
62 fsl,soc-operating-points = <
63 /* ARM kHz SOC-PU uV */
68 clock-latency = <61036>; /* two CLK32 periods */
69 #cooling-cells = <2>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
77 arm-supply = <®_arm>;
78 pu-supply = <®_pu>;
79 soc-supply = <®_soc>;
85 compatible = "mmio-sram";
103 i2c4: i2c@21f8000 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
115 capture-subsystem {
116 compatible = "fsl,imx-capture-subsystem";
120 display-subsystem {
121 compatible = "fsl,imx-display-subsystem";
127 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
137 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
145 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
150 gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
158 gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
165 gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
174 gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
181 compatible = "video-mux";
182 mux-controls = <&mux 0>;
183 #address-cells = <1>;
184 #size-cells = <0>;
190 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
198 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
206 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
214 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
229 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
235 compatible = "video-mux";
236 mux-controls = <&mux 1>;
237 #address-cells = <1>;
238 #size-cells = <0>;
244 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
252 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
260 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
268 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
283 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
290 compatible = "fsl,imx6dl-gpt";
294 compatible = "fsl,imx6dl-hdmi";
298 compatible = "fsl,imx6dl-iomuxc";
303 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
311 clock-names = "di0_pll", "di1_pll",
319 #address-cells = <1>;
320 #size-cells = <0>;
324 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
329 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
335 #address-cells = <1>;
336 #size-cells = <0>;
340 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
345 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
351 #address-cells = <1>;
352 #size-cells = <0>;
356 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
361 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
367 #address-cells = <1>;
368 #size-cells = <0>;
372 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
377 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
383 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
393 compatible = "fsl,imx6dl-vpu", "cnm,coda960";