Lines Matching +full:0 +full:x80000000
15 reg = <0x70000000 0x40000000>; /* Up to 1GiB */
21 #size-cells = <0>;
23 reg_3p3v: regulator@0 {
25 reg = <0>;
36 pinctrl-0 = <&pinctrl_esdhc2>,
46 pinctrl-0 = <&pinctrl_uart3>;
52 pinctrl-0 = <&pinctrl_ecspi1>;
60 pinctrl-0 = <&pinctrl_esdhc3>;
69 pinctrl-0 = <&pinctrl_hog>;
74 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
75 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
76 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
77 MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
78 MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
79 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
80 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
81 MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
82 MX53_PAD_GPIO_3__GPIO1_3 0x80000000
83 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
84 MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
90 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
91 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
92 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
93 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
99 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
100 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
106 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
107 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
113 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
114 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
115 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
121 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
122 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
123 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
129 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
130 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
131 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
132 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
133 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
134 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
140 MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
141 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
147 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
148 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
149 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
150 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
151 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
152 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
153 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
154 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
155 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
156 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
162 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
163 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
164 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
165 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
166 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
167 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
168 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
169 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
170 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
171 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
177 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
178 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
184 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
185 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
191 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4
192 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4
198 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4
199 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
205 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1e4
206 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1e4
222 pinctrl-0 = <&pinctrl_uart1>;
229 pinctrl-0 = <&pinctrl_uart2>;
235 pinctrl-0 = <&pinctrl_can1>;
241 pinctrl-0 = <&pinctrl_can2>;
247 pinctrl-0 = <&pinctrl_i2c3>;
253 pinctrl-0 = <&pinctrl_cspi>;
261 pinctrl-0 = <&pinctrl_i2c2>;
266 reg = <0x8>;
274 reg = <0x48>;
280 reg = <0x50>;
286 pinctrl-0 = <&pinctrl_fec>;