Lines Matching +full:0 +full:x5
15 reg = <0x70000000 0x20000000>,
16 <0xb0000000 0x20000000>;
22 pinctrl-0 = <&pinctrl_ipu_disp0>;
25 #size-cells = <0>;
28 port@0 {
29 reg = <0>;
72 pinctrl-0 = <&led_pin_gpio7_7>;
76 gpios = <&gpio7 7 0>;
94 #size-cells = <0>;
96 reg_3p2v: regulator@0 {
98 reg = <0>;
111 gpio = <&gpio7 8 0>;
144 pinctrl-0 = <&pinctrl_esdhc1>;
158 pinctrl-0 = <&pinctrl_esdhc3>;
167 pinctrl-0 = <&pinctrl_hog>;
172 MX53_PAD_GPIO_8__GPIO1_8 0x80000000
173 MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
174 MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
175 MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
176 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
177 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
178 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
179 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
185 MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
191 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
192 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
193 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
194 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
200 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4
206 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
207 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
208 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
209 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
210 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
211 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
217 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
218 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
219 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
220 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
221 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
222 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
223 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
224 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
225 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
226 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
232 MX53_PAD_FEC_MDC__FEC_MDC 0x4
233 MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
234 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
235 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
236 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
237 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
238 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
239 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
240 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
241 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
248 MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
249 MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
255 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
256 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
262 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
263 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
264 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
265 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
266 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
267 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
268 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
269 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
270 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
271 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
272 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
273 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
274 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
275 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
276 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
277 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
278 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
279 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
280 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
281 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
282 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
283 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
284 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
285 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
286 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
287 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
288 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
289 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
296 MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
297 MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
303 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
304 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
312 pinctrl-0 = <&pinctrl_vga_sync>;
322 pinctrl-0 = <&pinctrl_uart1>;
328 pinctrl-0 = <&pinctrl_i2c2>;
333 reg = <0x0a>;
335 pinctrl-0 = <&pinctrl_codec>;
336 #sound-dai-cells = <0>;
345 pinctrl-0 = <&pinctrl_i2c1>;
350 reg = <0x1c>;
356 pinctrl-0 = <&pinctrl_audmux>;
362 pinctrl-0 = <&pinctrl_fec>;