Lines Matching full:clks
83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
145 clocks = <&clks IMX5_CLK_IPU_GATE>,
146 <&clks IMX5_CLK_IPU_DI0_GATE>,
147 <&clks IMX5_CLK_IPU_DI1_GATE>;
192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
193 <&clks IMX5_CLK_DUMMY>,
194 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
203 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
204 <&clks IMX5_CLK_DUMMY>,
205 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
215 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
216 <&clks IMX5_CLK_UART3_PER_GATE>;
227 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
228 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
238 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
239 <&clks IMX5_CLK_SSI2_ROOT_GATE>;
252 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
253 <&clks IMX5_CLK_DUMMY>,
254 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
264 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
265 <&clks IMX5_CLK_DUMMY>,
266 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
292 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
302 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
312 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
322 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
369 clocks = <&clks IMX5_CLK_DUMMY>;
377 clocks = <&clks IMX5_CLK_DUMMY>;
384 clocks = <&clks IMX5_CLK_DUMMY>;
392 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
393 <&clks IMX5_CLK_GPT_HF_GATE>;
406 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
407 <&clks IMX5_CLK_PWM1_HF_GATE>;
416 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
417 <&clks IMX5_CLK_PWM2_HF_GATE>;
426 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
427 <&clks IMX5_CLK_UART1_PER_GATE>;
436 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
437 <&clks IMX5_CLK_UART2_PER_GATE>;
449 clks: ccm@73fd4000{ label
473 clocks = <&clks IMX5_CLK_IIM_GATE>;
485 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
495 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
496 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
505 clocks = <&clks IMX5_CLK_SDMA_GATE>,
506 <&clks IMX5_CLK_AHB>;
518 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
519 <&clks IMX5_CLK_CSPI_IPG_GATE>;
530 clocks = <&clks IMX5_CLK_I2C2_GATE>;
540 clocks = <&clks IMX5_CLK_I2C1_GATE>;
549 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
550 <&clks IMX5_CLK_SSI1_ROOT_GATE>;
562 clocks = <&clks IMX5_CLK_DUMMY>;
577 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
595 clocks = <&clks IMX5_CLK_NFC_GATE>;
603 clocks = <&clks IMX5_CLK_PATA_GATE>;
612 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
613 <&clks IMX5_CLK_SSI3_ROOT_GATE>;
626 clocks = <&clks IMX5_CLK_FEC_GATE>,
627 <&clks IMX5_CLK_FEC_GATE>,
628 <&clks IMX5_CLK_FEC_GATE>;
637 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
638 <&clks IMX5_CLK_VPU_GATE>;
648 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>,
649 <&clks IMX5_CLK_SAHARA_IPG_GATE>;