Lines Matching +full:0 +full:x80000000
20 reg = <0x90000000 0x20000000>;
32 pinctrl-0 = <&pinctrl_fec>;
34 phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
43 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
44 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
45 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
46 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
47 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
48 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
49 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
50 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
51 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
52 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
53 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
54 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
55 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
56 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
57 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
58 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
59 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
60 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
66 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
67 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
82 pinctrl-0 = <&pinctrl_uart3>;