Lines Matching +full:0 +full:x8006a000
43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 87 86 0 0>;
98 reg = <0x80006000 0x800>;
107 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
120 #size-cells = <0>;
121 reg = <0x80010000 0x2000>;
124 dmas = <&dma_apbh 0>;
131 #size-cells = <0>;
132 reg = <0x80012000 0x2000>;
142 #size-cells = <0>;
143 reg = <0x80014000 0x2000>;
153 #size-cells = <0>;
154 reg = <0x80016000 0x2000>;
164 #size-cells = <0>;
166 reg = <0x80018000 0x2000>;
168 gpio0: gpio@0 {
170 reg = <0>;
218 duart_pins_a: duart@0 {
219 reg = <0>;
240 duart_4pins_a: duart-4pins@0 {
241 reg = <0>;
253 gpmi_pins_a: gpmi-nand@0 {
254 reg = <0>;
277 gpmi_status_cfg: gpmi-status-cfg@0 {
278 reg = <0>;
287 auart0_pins_a: auart0@0 {
288 reg = <0>;
300 auart0_2pins_a: auart0-2pins@0 {
301 reg = <0>;
311 auart1_pins_a: auart1@0 {
312 reg = <0>;
324 auart1_2pins_a: auart1-2pins@0 {
325 reg = <0>;
335 auart2_2pins_a: auart2-2pins@0 {
336 reg = <0>;
357 auart2_pins_a: auart2-pins@0 {
358 reg = <0>;
370 auart3_pins_a: auart3@0 {
371 reg = <0>;
383 auart3_2pins_a: auart3-2pins@0 {
384 reg = <0>;
405 auart4_2pins_a: auart4@0 {
406 reg = <0>;
427 mac0_pins_a: mac0@0 {
428 reg = <0>;
471 mac1_pins_a: mac1@0 {
472 reg = <0>;
486 mmc0_8bit_pins_a: mmc0-8bit@0 {
487 reg = <0>;
506 mmc0_4bit_pins_a: mmc0-4bit@0 {
507 reg = <0>;
522 mmc0_cd_cfg: mmc0-cd-cfg@0 {
523 reg = <0>;
530 mmc0_sck_cfg: mmc0-sck-cfg@0 {
531 reg = <0>;
539 mmc1_4bit_pins_a: mmc1-4bit@0 {
540 reg = <0>;
555 mmc1_cd_cfg: mmc1-cd-cfg@0 {
556 reg = <0>;
563 mmc1_sck_cfg: mmc1-sck-cfg@0 {
564 reg = <0>;
573 mmc2_4bit_pins_a: mmc2-4bit@0 {
574 reg = <0>;
605 mmc2_cd_cfg: mmc2-cd-cfg@0 {
606 reg = <0>;
613 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
614 reg = <0>;
631 i2c0_pins_a: i2c0@0 {
632 reg = <0>;
653 i2c1_pins_a: i2c1@0 {
654 reg = <0>;
675 saif0_pins_a: saif0@0 {
676 reg = <0>;
700 saif1_pins_a: saif1@0 {
701 reg = <0>;
710 pwm0_pins_a: pwm0@0 {
711 reg = <0>;
720 pwm2_pins_a: pwm2@0 {
721 reg = <0>;
730 pwm3_pins_a: pwm3@0 {
731 reg = <0>;
750 pwm4_pins_a: pwm4@0 {
751 reg = <0>;
760 lcdif_24bit_pins_a: lcdif-24bit@0 {
761 reg = <0>;
793 lcdif_18bit_pins_a: lcdif-18bit@0 {
794 reg = <0>;
820 lcdif_16bit_pins_a: lcdif-16bit@0 {
821 reg = <0>;
845 lcdif_sync_pins_a: lcdif-sync@0 {
846 reg = <0>;
858 can0_pins_a: can0@0 {
859 reg = <0>;
869 can1_pins_a: can1@0 {
870 reg = <0>;
880 spi2_pins_a: spi2@0 {
881 reg = <0>;
893 spi3_pins_a: spi3@0 {
894 reg = <0>;
921 usb0_pins_a: usb0@0 {
922 reg = <0>;
941 usb1_pins_a: usb1@0 {
942 reg = <0>;
951 usb0_id_pins_a: usb0id@0 {
952 reg = <0>;
961 usb0_id_pins_b: usb0id1@0 {
962 reg = <0>;
975 reg = <0x8001c000 0x2000>;
981 reg = <0x80022000 0x2000>;
987 reg = <0x80024000 0x2000>;
988 interrupts = <78 79 66 0
1003 reg = <0x80028000 0x2000>;
1009 reg = <0x8002a000 0x2000>;
1018 reg = <0x8002c000 0x2000>;
1023 reg = <0x8002e000 0x2000>;
1029 reg = <0x80030000 0x2000>;
1039 reg = <0x80032000 0x2000>;
1048 reg = <0x80034000 0x2000>;
1056 reg = <0x8003c000 0x200>;
1061 reg = <0x8003c200 0x100>;
1066 reg = <0x8003c300 0x100>;
1071 reg = <0x8003c400 0x100>;
1076 reg = <0x8003c500 0x100>;
1081 reg = <0x8003c700 0x100>;
1086 reg = <0x8003c800 0x100>;
1095 reg = <0x80040000 0x40000>;
1100 reg = <0x80040000 0x2000>;
1105 #sound-dai-cells = <0>;
1107 reg = <0x80042000 0x2000>;
1109 #clock-cells = <0>;
1117 reg = <0x80044000 0x2000>;
1122 #sound-dai-cells = <0>;
1124 reg = <0x80046000 0x2000>;
1134 reg = <0x80050000 0x2000>;
1143 reg = <0x80054000 0x2000>;
1152 reg = <0x80056000 0x2000>;
1158 #size-cells = <0>;
1160 reg = <0x80058000 0x2000>;
1170 #size-cells = <0>;
1172 reg = <0x8005a000 0x2000>;
1182 reg = <0x80064000 0x2000>;
1191 reg = <0x80068000 0x2000>;
1198 reg = <0x8006a000 0x2000>;
1208 reg = <0x8006c000 0x2000>;
1218 reg = <0x8006e000 0x2000>;
1228 reg = <0x80070000 0x2000>;
1238 reg = <0x80072000 0x2000>;
1240 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1248 reg = <0x80074000 0x1000>;
1257 reg = <0x8007c000 0x2000>;
1264 reg = <0x8007e000 0x2000>;
1275 reg = <0x80080000 0x80000>;
1280 reg = <0x80080000 0x10000>;
1289 reg = <0x80090000 0x10000>;
1298 reg = <0x800c0000 0x10000>;
1304 reg = <0x800f0000 0x4000>;
1313 reg = <0x800f4000 0x4000>;
1321 reg = <0x800f8000 0x8000>;