Lines Matching +full:0 +full:x10000
35 #size-cells = <0>;
37 cpu@0 {
40 reg = <0x0>;
47 reg = <0x1>;
54 reg = <0x100>;
61 reg = <0x101>;
68 reg = <0x102>;
75 reg = <0x103>;
88 reg = <0x10010000 0x10000>;
94 reg = <0x10200000 0x10000>;
100 reg = <0x10600000 0x10000>;
106 reg = <0x10700000 0x10000>;
112 reg = <0x10A00000 0x10000>;
118 reg = <0x10CE0000 0x10000>;
124 reg = <0x11090000 0x10000>;
130 reg = <0x11830000 0x10000>;
136 reg = <0x122E0000 0x10000>;
142 reg = <0x128C0000 0x10000>;
148 reg = <0x133C0000 0x10000>;
154 reg = <0x13F00000 0x10000>;
160 reg = <0x14550000 0x10000>;
168 reg = <0x10481000 0x1000>,
169 <0x10482000 0x2000>,
170 <0x10484000 0x2000>,
171 <0x10486000 0x2000>;
178 reg = <0x10000000 0x100>;
183 reg = <0x100B0000 0x1000>;
204 reg = <0x10F00000 0x1000>;
205 ranges = <0x0 0x10F00000 0x6000>;
210 reg = <0x4000 0x1000>;
216 reg = <0x5000 0x1000>;
222 reg = <0x11600000 0x1000>;
234 reg = <0x12290000 0x1000>;
240 reg = <0x128B0000 0x1000>;
246 reg = <0x10D50000 0x10000>;
251 reg = <0x12C00000 0x100>;
260 reg = <0x12C10000 0x100>;
269 reg = <0x12C20000 0x100>;
278 reg = <0x12860000 0x100>;
287 reg = <0x12140000 0x2000>;
290 #size-cells = <0>;
300 assigned-clock-rates = <0>, <0>, <800000000>;
307 reg = <0x12150000 0x2000>;
310 #size-cells = <0>;
320 assigned-clock-rates = <0>, <0>, <800000000>;
327 reg = <0x12160000 0x2000>;
330 #size-cells = <0>;
340 assigned-clock-rates = <0>, <0>, <800000000>;
347 reg = <0x12DA0000 0x1000>;
350 #size-cells = <0>;
352 pinctrl-0 = <&i2c0_hs_bus>;
360 reg = <0x12DB0000 0x1000>;
363 #size-cells = <0>;
365 pinctrl-0 = <&i2c1_hs_bus>;
373 reg = <0x12DC0000 0x1000>;
376 #size-cells = <0>;
378 pinctrl-0 = <&i2c2_hs_bus>;
386 reg = <0x12DD0000 0x1000>;
389 #size-cells = <0>;
391 pinctrl-0 = <&i2c3_hs_bus>;