Lines Matching +full:opp +full:- +full:350000000
1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a9";
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
50 compatible = "arm,cortex-a9";
53 clock-names = "cpu";
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
60 compatible = "arm,cortex-a9";
63 clock-names = "cpu";
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
70 compatible = "arm,cortex-a9";
73 clock-names = "cpu";
74 operating-points-v2 = <&cpu0_opp_table>;
75 #cooling-cells = <2>; /* min followed by max */
79 cpu0_opp_table: opp-table0 {
80 compatible = "operating-points-v2";
81 opp-shared;
83 opp-200000000 {
84 opp-hz = /bits/ 64 <200000000>;
85 opp-microvolt = <900000>;
86 clock-latency-ns = <200000>;
88 opp-300000000 {
89 opp-hz = /bits/ 64 <300000000>;
90 opp-microvolt = <900000>;
91 clock-latency-ns = <200000>;
93 opp-400000000 {
94 opp-hz = /bits/ 64 <400000000>;
95 opp-microvolt = <925000>;
96 clock-latency-ns = <200000>;
98 opp-500000000 {
99 opp-hz = /bits/ 64 <500000000>;
100 opp-microvolt = <950000>;
101 clock-latency-ns = <200000>;
103 opp-600000000 {
104 opp-hz = /bits/ 64 <600000000>;
105 opp-microvolt = <975000>;
106 clock-latency-ns = <200000>;
108 opp-700000000 {
109 opp-hz = /bits/ 64 <700000000>;
110 opp-microvolt = <987500>;
111 clock-latency-ns = <200000>;
113 opp-800000000 {
114 opp-hz = /bits/ 64 <800000000>;
115 opp-microvolt = <1000000>;
116 clock-latency-ns = <200000>;
117 opp-suspend;
119 opp-900000000 {
120 opp-hz = /bits/ 64 <900000000>;
121 opp-microvolt = <1037500>;
122 clock-latency-ns = <200000>;
124 opp-1000000000 {
125 opp-hz = /bits/ 64 <1000000000>;
126 opp-microvolt = <1087500>;
127 clock-latency-ns = <200000>;
129 opp-1100000000 {
130 opp-hz = /bits/ 64 <1100000000>;
131 opp-microvolt = <1137500>;
132 clock-latency-ns = <200000>;
134 opp-1200000000 {
135 opp-hz = /bits/ 64 <1200000000>;
136 opp-microvolt = <1187500>;
137 clock-latency-ns = <200000>;
139 opp-1300000000 {
140 opp-hz = /bits/ 64 <1300000000>;
141 opp-microvolt = <1250000>;
142 clock-latency-ns = <200000>;
144 opp-1400000000 {
145 opp-hz = /bits/ 64 <1400000000>;
146 opp-microvolt = <1287500>;
147 clock-latency-ns = <200000>;
149 cpu0_opp_1500: opp-1500000000 {
150 opp-hz = /bits/ 64 <1500000000>;
151 opp-microvolt = <1350000>;
152 clock-latency-ns = <200000>;
153 turbo-mode;
161 compatible = "samsung,exynos4x12-pinctrl";
167 compatible = "samsung,exynos4x12-pinctrl";
171 wakup_eint: wakeup-interrupt-controller {
172 compatible = "samsung,exynos4210-wakeup-eint";
173 interrupt-parent = <&gic>;
179 compatible = "samsung,exynos4x12-pinctrl";
181 interrupt-parent = <&combiner>;
186 compatible = "samsung,exynos4x12-pinctrl";
192 compatible = "mmio-sram";
194 #address-cells = <1>;
195 #size-cells = <1>;
198 smp-sram@0 {
199 compatible = "samsung,exynos4210-sysram";
203 smp-sram@2f000 {
204 compatible = "samsung,exynos4210-sysram-ns";
209 pd_isp: power-domain@10023ca0 {
210 compatible = "samsung,exynos4210-pd";
212 #power-domain-cells = <0>;
216 l2c: cache-controller@10502000 {
217 compatible = "arm,pl310-cache";
219 cache-unified;
220 cache-level = <2>;
221 prefetch-data = <1>;
222 prefetch-instr = <1>;
223 arm,tag-latency = <2 2 1>;
224 arm,data-latency = <3 2 1>;
225 arm,double-linefill = <1>;
226 arm,double-linefill-incr = <0>;
227 arm,double-linefill-wrap = <1>;
228 arm,prefetch-drop = <1>;
229 arm,prefetch-offset = <7>;
232 clock: clock-controller@10030000 {
233 compatible = "samsung,exynos4412-clock";
235 #clock-cells = <1>;
238 isp_clock: clock-controller@10048000 {
239 compatible = "samsung,exynos4412-isp-clock";
241 #clock-cells = <1>;
242 power-domains = <&pd_isp>;
245 clock-names = "aclk200", "aclk400_mcuisp";
249 compatible = "samsung,exynos4412-mct";
252 clock-names = "fin_pll", "mct";
253 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
261 compatible = "samsung,exynos5250-wdt";
265 clock-names = "watchdog";
266 samsung,syscon-phandle = <&pmu_system_controller>;
270 compatible = "samsung,exynos4212-adc";
272 interrupt-parent = <&combiner>;
275 clock-names = "adc";
276 #io-channel-cells = <1>;
277 io-channel-ranges;
278 samsung,syscon-phandle = <&pmu_system_controller>;
283 compatible = "samsung,exynos4212-g2d";
287 clock-names = "sclk_fimg2d", "fimg2d";
292 compatible = "samsung,exynos4412-dw-mshc";
295 #address-cells = <1>;
296 #size-cells = <0>;
297 fifo-depth = <0x80>;
299 clock-names = "biu", "ciu";
304 compatible = "samsung,exynos-sysmmu";
306 interrupt-parent = <&combiner>;
308 clock-names = "sysmmu", "master";
310 #iommu-cells = <0>;
314 compatible = "samsung,exynos-sysmmu";
316 interrupt-parent = <&combiner>;
318 power-domains = <&pd_isp>;
319 clock-names = "sysmmu";
321 #iommu-cells = <0>;
325 compatible = "samsung,exynos-sysmmu";
327 interrupt-parent = <&combiner>;
329 power-domains = <&pd_isp>;
330 clock-names = "sysmmu";
332 #iommu-cells = <0>;
336 compatible = "samsung,exynos-sysmmu";
338 interrupt-parent = <&combiner>;
340 power-domains = <&pd_isp>;
341 clock-names = "sysmmu";
343 #iommu-cells = <0>;
347 compatible = "samsung,exynos-sysmmu";
349 interrupt-parent = <&combiner>;
351 power-domains = <&pd_isp>;
352 clock-names = "sysmmu";
354 #iommu-cells = <0>;
358 compatible = "samsung,exynos-sysmmu";
360 interrupt-parent = <&combiner>;
362 power-domains = <&pd_isp>;
363 clock-names = "sysmmu", "master";
366 #iommu-cells = <0>;
370 compatible = "samsung,exynos-sysmmu";
372 interrupt-parent = <&combiner>;
374 power-domains = <&pd_isp>;
375 clock-names = "sysmmu", "master";
378 #iommu-cells = <0>;
382 compatible = "samsung,exynos-bus";
384 clock-names = "bus";
385 operating-points-v2 = <&bus_dmc_opp_table>;
390 compatible = "samsung,exynos-bus";
392 clock-names = "bus";
393 operating-points-v2 = <&bus_acp_opp_table>;
398 compatible = "samsung,exynos-bus";
400 clock-names = "bus";
401 operating-points-v2 = <&bus_dmc_opp_table>;
405 bus_dmc_opp_table: opp-table1 {
406 compatible = "operating-points-v2";
407 opp-shared;
409 opp-100000000 {
410 opp-hz = /bits/ 64 <100000000>;
411 opp-microvolt = <900000>;
413 opp-134000000 {
414 opp-hz = /bits/ 64 <134000000>;
415 opp-microvolt = <900000>;
417 opp-160000000 {
418 opp-hz = /bits/ 64 <160000000>;
419 opp-microvolt = <900000>;
421 opp-267000000 {
422 opp-hz = /bits/ 64 <267000000>;
423 opp-microvolt = <950000>;
425 opp-400000000 {
426 opp-hz = /bits/ 64 <400000000>;
427 opp-microvolt = <1050000>;
428 opp-suspend;
432 bus_acp_opp_table: opp-table2 {
433 compatible = "operating-points-v2";
434 opp-shared;
436 opp-100000000 {
437 opp-hz = /bits/ 64 <100000000>;
439 opp-134000000 {
440 opp-hz = /bits/ 64 <134000000>;
442 opp-160000000 {
443 opp-hz = /bits/ 64 <160000000>;
445 opp-267000000 {
446 opp-hz = /bits/ 64 <267000000>;
451 compatible = "samsung,exynos-bus";
453 clock-names = "bus";
454 operating-points-v2 = <&bus_leftbus_opp_table>;
459 compatible = "samsung,exynos-bus";
461 clock-names = "bus";
462 operating-points-v2 = <&bus_leftbus_opp_table>;
467 compatible = "samsung,exynos-bus";
469 clock-names = "bus";
470 operating-points-v2 = <&bus_display_opp_table>;
475 compatible = "samsung,exynos-bus";
477 clock-names = "bus";
478 operating-points-v2 = <&bus_fsys_opp_table>;
483 compatible = "samsung,exynos-bus";
485 clock-names = "bus";
486 operating-points-v2 = <&bus_peri_opp_table>;
491 compatible = "samsung,exynos-bus";
493 clock-names = "bus";
494 operating-points-v2 = <&bus_leftbus_opp_table>;
498 bus_leftbus_opp_table: opp-table3 {
499 compatible = "operating-points-v2";
500 opp-shared;
502 opp-100000000 {
503 opp-hz = /bits/ 64 <100000000>;
504 opp-microvolt = <900000>;
506 opp-134000000 {
507 opp-hz = /bits/ 64 <134000000>;
508 opp-microvolt = <925000>;
510 opp-160000000 {
511 opp-hz = /bits/ 64 <160000000>;
512 opp-microvolt = <950000>;
514 opp-200000000 {
515 opp-hz = /bits/ 64 <200000000>;
516 opp-microvolt = <1000000>;
517 opp-suspend;
521 bus_display_opp_table: opp-table4 {
522 compatible = "operating-points-v2";
523 opp-shared;
525 opp-160000000 {
526 opp-hz = /bits/ 64 <160000000>;
528 opp-200000000 {
529 opp-hz = /bits/ 64 <200000000>;
533 bus_fsys_opp_table: opp-table5 {
534 compatible = "operating-points-v2";
535 opp-shared;
537 opp-100000000 {
538 opp-hz = /bits/ 64 <100000000>;
540 opp-134000000 {
541 opp-hz = /bits/ 64 <134000000>;
545 bus_peri_opp_table: opp-table6 {
546 compatible = "operating-points-v2";
547 opp-shared;
549 opp-50000000 {
550 opp-hz = /bits/ 64 <50000000>;
552 opp-100000000 {
553 opp-hz = /bits/ 64 <100000000>;
560 samsung,combiner-nr = <20>;
586 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
588 /* fimc_[0-3] are configured outside, under phandles */
589 fimc_lite_0: fimc-lite@12390000 {
590 compatible = "samsung,exynos4212-fimc-lite";
593 power-domains = <&pd_isp>;
595 clock-names = "flite";
600 fimc_lite_1: fimc-lite@123a0000 {
601 compatible = "samsung,exynos4212-fimc-lite";
604 power-domains = <&pd_isp>;
606 clock-names = "flite";
611 fimc_is: fimc-is@12000000 {
612 compatible = "samsung,exynos4212-fimc-is";
616 power-domains = <&pd_isp>;
638 clock-names = "lite0", "lite1", "ppmuispx",
648 iommu-names = "isp", "drc", "fd", "mcuctl";
649 #address-cells = <1>;
650 #size-cells = <1>;
658 i2c1_isp: i2c-isp@12140000 {
659 compatible = "samsung,exynos4212-i2c-isp";
662 clock-names = "i2c_isp";
663 #address-cells = <1>;
664 #size-cells = <0>;
670 compatible = "samsung,exynos4x12-usb2-phy";
671 samsung,sysreg-phandle = <&sys_reg>;
675 compatible = "samsung,exynos4212-fimc";
676 samsung,pix-limits = <4224 8192 1920 4224>;
677 samsung,mainscaler-ext;
678 samsung,isp-wb;
679 samsung,cam-if;
683 compatible = "samsung,exynos4212-fimc";
684 samsung,pix-limits = <4224 8192 1920 4224>;
685 samsung,mainscaler-ext;
686 samsung,isp-wb;
687 samsung,cam-if;
691 compatible = "samsung,exynos4212-fimc";
692 samsung,pix-limits = <4224 8192 1920 4224>;
693 samsung,mainscaler-ext;
694 samsung,isp-wb;
695 samsung,lcd-wb;
696 samsung,cam-if;
700 compatible = "samsung,exynos4212-fimc";
701 samsung,pix-limits = <1920 8192 1366 1920>;
703 samsung,mainscaler-ext;
704 samsung,isp-wb;
705 samsung,lcd-wb;
709 cpu-offset = <0x4000>;
724 interrupt-names = "gp",
735 operating-points-v2 = <&gpu_opp_table>;
737 gpu_opp_table: opp-table {
738 compatible = "operating-points-v2";
740 opp-160000000 {
741 opp-hz = /bits/ 64 <160000000>;
742 opp-microvolt = <875000>;
744 opp-267000000 {
745 opp-hz = /bits/ 64 <267000000>;
746 opp-microvolt = <900000>;
748 opp-350000000 {
749 opp-hz = /bits/ 64 <350000000>;
750 opp-microvolt = <950000>;
752 opp-440000000 {
753 opp-hz = /bits/ 64 <440000000>;
754 opp-microvolt = <1025000>;
760 compatible = "samsung,exynos4212-hdmi";
764 compatible = "samsung,exynos4212-jpeg";
768 compatible = "samsung,exynos4212-rotator";
772 compatible = "samsung,exynos4212-mixer";
773 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
780 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
785 compatible = "samsung,exynos4412-pmu", "syscon";
786 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
791 #clock-cells = <1>;
795 compatible = "samsung,exynos4412-tmu";
796 interrupt-parent = <&combiner>;
800 clock-names = "tmu_apbif";
804 #include "exynos4412-pinctrl.dtsi"