Lines Matching +full:opp +full:- +full:400000000
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,cortex-a9";
40 clock-names = "cpu";
41 clock-latency = <160000>;
43 operating-points = <
51 #cooling-cells = <2>; /* min followed by max */
56 compatible = "arm,cortex-a9";
59 clock-names = "cpu";
60 clock-latency = <160000>;
62 operating-points = <
70 #cooling-cells = <2>; /* min followed by max */
76 compatible = "mmio-sram";
78 #address-cells = <1>;
79 #size-cells = <1>;
82 smp-sram@0 {
83 compatible = "samsung,exynos4210-sysram";
87 smp-sram@1f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
93 pd_lcd1: power-domain@10023ca0 {
94 compatible = "samsung,exynos4210-pd";
96 #power-domain-cells = <0>;
100 l2c: cache-controller@10502000 {
101 compatible = "arm,pl310-cache";
103 cache-unified;
104 cache-level = <2>;
105 prefetch-data = <1>;
106 prefetch-instr = <1>;
107 arm,tag-latency = <2 2 1>;
108 arm,data-latency = <2 2 1>;
112 compatible = "samsung,exynos4210-mct";
115 clock-names = "fin_pll", "mct";
116 interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
125 compatible = "samsung,s3c6410-wdt";
129 clock-names = "watchdog";
132 clock: clock-controller@10030000 {
133 compatible = "samsung,exynos4210-clock";
135 #clock-cells = <1>;
139 compatible = "samsung,exynos4210-pinctrl";
145 compatible = "samsung,exynos4210-pinctrl";
149 wakup_eint: wakeup-interrupt-controller {
150 compatible = "samsung,exynos4210-wakeup-eint";
151 interrupt-parent = <&gic>;
157 compatible = "samsung,exynos4210-pinctrl";
162 compatible = "samsung,s5pv210-g2d";
166 clock-names = "sclk_fimg2d", "fimg2d";
167 power-domains = <&pd_lcd0>;
172 compatible = "samsung,exynos-ppmu";
178 compatible = "samsung,exynos-ppmu";
181 clock-names = "ppmu";
186 compatible = "samsung,exynos-sysmmu";
188 interrupt-parent = <&combiner>;
190 clock-names = "sysmmu", "master";
192 power-domains = <&pd_lcd0>;
193 #iommu-cells = <0>;
197 compatible = "samsung,exynos-sysmmu";
198 interrupt-parent = <&combiner>;
201 clock-names = "sysmmu", "master";
203 power-domains = <&pd_lcd1>;
204 #iommu-cells = <0>;
208 compatible = "samsung,exynos-bus";
210 clock-names = "bus";
211 operating-points-v2 = <&bus_dmc_opp_table>;
216 compatible = "samsung,exynos-bus";
218 clock-names = "bus";
219 operating-points-v2 = <&bus_acp_opp_table>;
224 compatible = "samsung,exynos-bus";
226 clock-names = "bus";
227 operating-points-v2 = <&bus_peri_opp_table>;
232 compatible = "samsung,exynos-bus";
234 clock-names = "bus";
235 operating-points-v2 = <&bus_fsys_opp_table>;
240 compatible = "samsung,exynos-bus";
242 clock-names = "bus";
243 operating-points-v2 = <&bus_display_opp_table>;
248 compatible = "samsung,exynos-bus";
250 clock-names = "bus";
251 operating-points-v2 = <&bus_leftbus_opp_table>;
256 compatible = "samsung,exynos-bus";
258 clock-names = "bus";
259 operating-points-v2 = <&bus_leftbus_opp_table>;
264 compatible = "samsung,exynos-bus";
266 clock-names = "bus";
267 operating-points-v2 = <&bus_leftbus_opp_table>;
272 compatible = "samsung,exynos-bus";
274 clock-names = "bus";
275 operating-points-v2 = <&bus_leftbus_opp_table>;
280 compatible = "operating-points-v2";
281 opp-shared;
283 opp-134000000 {
284 opp-hz = /bits/ 64 <134000000>;
285 opp-microvolt = <1025000>;
287 opp-267000000 {
288 opp-hz = /bits/ 64 <267000000>;
289 opp-microvolt = <1050000>;
291 opp-400000000 {
292 opp-hz = /bits/ 64 <400000000>;
293 opp-microvolt = <1150000>;
294 opp-suspend;
299 compatible = "operating-points-v2";
300 opp-shared;
302 opp-134000000 {
303 opp-hz = /bits/ 64 <134000000>;
305 opp-160000000 {
306 opp-hz = /bits/ 64 <160000000>;
308 opp-200000000 {
309 opp-hz = /bits/ 64 <200000000>;
314 compatible = "operating-points-v2";
315 opp-shared;
317 opp-5000000 {
318 opp-hz = /bits/ 64 <5000000>;
320 opp-100000000 {
321 opp-hz = /bits/ 64 <100000000>;
326 compatible = "operating-points-v2";
327 opp-shared;
329 opp-10000000 {
330 opp-hz = /bits/ 64 <10000000>;
332 opp-134000000 {
333 opp-hz = /bits/ 64 <134000000>;
338 compatible = "operating-points-v2";
339 opp-shared;
341 opp-100000000 {
342 opp-hz = /bits/ 64 <100000000>;
344 opp-134000000 {
345 opp-hz = /bits/ 64 <134000000>;
347 opp-160000000 {
348 opp-hz = /bits/ 64 <160000000>;
353 compatible = "operating-points-v2";
354 opp-shared;
356 opp-100000000 {
357 opp-hz = /bits/ 64 <100000000>;
359 opp-160000000 {
360 opp-hz = /bits/ 64 <160000000>;
362 opp-200000000 {
363 opp-hz = /bits/ 64 <200000000>;
364 opp-suspend;
383 polling-delay-passive = <0>;
384 polling-delay = <0>;
385 thermal-sensors = <&tmu 0>;
389 cpu-offset = <0x8000>;
395 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
399 samsung,combiner-nr = <16>;
419 samsung,pix-limits = <4224 8192 1920 4224>;
420 samsung,mainscaler-ext;
421 samsung,cam-if;
425 samsung,pix-limits = <4224 8192 1920 4224>;
426 samsung,mainscaler-ext;
427 samsung,cam-if;
431 samsung,pix-limits = <4224 8192 1920 4224>;
432 samsung,mainscaler-ext;
433 samsung,lcd-wb;
437 samsung,pix-limits = <1920 8192 1366 1920>;
439 samsung,mainscaler-ext;
440 samsung,lcd-wb;
454 interrupt-names = "gp",
464 operating-points-v2 = <&gpu_opp_table>;
467 compatible = "operating-points-v2";
469 opp-160000000 {
470 opp-hz = /bits/ 64 <160000000>;
471 opp-microvolt = <950000>;
473 opp-267000000 {
474 opp-hz = /bits/ 64 <267000000>;
475 opp-microvolt = <1050000>;
481 power-domains = <&pd_lcd0>;
485 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
494 interrupt-affinity = <&cpu0>, <&cpu1>;
499 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
504 #clock-cells = <1>;
508 power-domains = <&pd_lcd0>;
512 power-domains = <&pd_lcd0>;
516 compatible = "samsung,exynos4210-tmu";
518 clock-names = "tmu_apbif";
523 #include "exynos4210-pinctrl.dtsi"