Lines Matching +full:0 +full:x41000000
49 reg = <0x41500000 0x100>;
54 reg = <0x48940000 0x4>,
55 <0x48940010 0x4>;
66 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
70 ranges = <0x0 0x48940000 0x20000>;
72 omap_dwc3_4: omap_dwc3_4@0 {
74 reg = <0 0x10000>;
83 reg = <0x10000 0x17000>;
98 reg = <0x41501000 0x4>,
99 <0x41501010 0x4>,
100 <0x41501014 0x4>;
108 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
112 ranges = <0x0 0x41501000 0x1000>;
116 mmu0_dsp2: mmu@0 {
118 reg = <0x0 0x100>;
120 #iommu-cells = <0>;
121 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
127 reg = <0x41502000 0x4>,
128 <0x41502010 0x4>,
129 <0x41502014 0x4>;
138 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
142 ranges = <0x0 0x41502000 0x1000>;
146 mmu1_dsp2: mmu@0 {
148 reg = <0x0 0x100>;
150 #iommu-cells = <0>;
151 ti,syscon-mmuconfig = <&dsp2_system 0x1>;
157 reg = <0x41000000 0x48000>,
158 <0x41600000 0x8000>,
159 <0x41700000 0x8000>;
161 ti,bootreg = <&scm_conf 0x560 10>;
164 resets = <&prm_dsp2 0>;
165 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
176 reg = <0 0x80>,
177 <0x4054 0x4>,
178 <0x4300 0x20>,
179 <0x9054 0x4>,
180 <0x9300 0x20>;