Lines Matching +full:mmu +full:- +full:500
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
48 compatible = "arm,armv7-timer";
53 interrupt-parent = <&gic>;
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
65 interrupt-parent = <&gic>;
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
73 interrupt-parent = <&gic>;
77 #address-cells = <1>;
78 #size-cells = <0>;
82 compatible = "arm,cortex-a15";
85 operating-points-v2 = <&cpu0_opp_table>;
88 clock-names = "cpu";
90 clock-latency = <300000>; /* From omap-cpufreq driver */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
116 opp-supported-hw = <0xFF 0x02>;
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
123 opp-supported-hw = <0xFF 0x04>;
132 compatible = "ti,omap-infra";
134 compatible = "ti,omap5-mpu";
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
155 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
170 compatible = "simple-bus";
171 #size-cells = <1>;
172 #address-cells = <1>;
175 dma-ranges;
182 reg-names = "rc_dbics", "ti_conf", "config";
184 #address-cells = <3>;
185 #size-cells = <2>;
189 bus-range = <0x00 0xff>;
190 #interrupt-cells = <1>;
191 num-lanes = <1>;
192 linux,pci-domain = <0>;
195 phy-names = "pcie-phy0";
196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
197 interrupt-map-mask = <0 0 0 7>;
198 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
204 pcie1_intc: interrupt-controller {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <1>;
213 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
215 num-lanes = <1>;
216 num-ib-windows = <4>;
217 num-ob-windows = <16>;
220 phy-names = "pcie-phy0";
221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
228 compatible = "simple-bus";
229 #size-cells = <1>;
230 #address-cells = <1>;
233 dma-ranges;
237 reg-names = "rc_dbics", "ti_conf", "config";
239 #address-cells = <3>;
240 #size-cells = <2>;
244 bus-range = <0x00 0xff>;
245 #interrupt-cells = <1>;
246 num-lanes = <1>;
247 linux,pci-domain = <1>;
250 phy-names = "pcie-phy0";
251 interrupt-map-mask = <0 0 0 7>;
252 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
257 pcie2_intc: interrupt-controller {
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <1>;
266 compatible = "mmio-sram";
269 #address-cells = <1>;
270 #size-cells = <1>;
282 sram-hs@0 {
283 compatible = "ti,secure-ram";
296 compatible = "mmio-sram";
299 #address-cells = <1>;
300 #size-cells = <1>;
305 compatible = "mmio-sram";
308 #address-cells = <1>;
309 #size-cells = <1>;
319 compatible = "ti,dra752-bandgap";
321 #thermal-sensor-cells = <1>;
330 compatible = "ti,dra7-iodelay";
332 #address-cells = <1>;
333 #size-cells = <0>;
334 #pinctrl-cells = <2>;
337 target-module@43300000 {
338 compatible = "ti,sysc-omap4", "ti,sysc";
340 reg-names = "rev";
342 clock-names = "fck";
343 #address-cells = <1>;
344 #size-cells = <1>;
348 compatible = "ti,edma3-tpcc";
350 reg-names = "edma3_cc";
354 interrupt-names = "edma3_ccint", "edma3_mperr",
356 dma-requests = <64>;
357 #dma-cells = <2>;
363 * ti,edma-memcpy-channels = <20 21>;
370 target-module@43400000 {
371 compatible = "ti,sysc-omap4", "ti,sysc";
373 reg-names = "rev";
375 clock-names = "fck";
376 #address-cells = <1>;
377 #size-cells = <1>;
381 compatible = "ti,edma3-tptc";
384 interrupt-names = "edma3_tcerrint";
388 target-module@43500000 {
389 compatible = "ti,sysc-omap4", "ti,sysc";
391 reg-names = "rev";
393 clock-names = "fck";
394 #address-cells = <1>;
395 #size-cells = <1>;
399 compatible = "ti,edma3-tptc";
402 interrupt-names = "edma3_tcerrint";
407 compatible = "ti,omap5-dmm";
414 compatible = "ti,dra7-ipu";
416 reg-names = "l2ram";
421 firmware-name = "dra7-ipu1-fw.xem4";
425 compatible = "ti,dra7-ipu";
427 reg-names = "l2ram";
432 firmware-name = "dra7-ipu2-fw.xem4";
436 compatible = "ti,dra7-dsp";
440 reg-names = "l2ram", "l1pram", "l1dram";
446 firmware-name = "dra7-dsp1-fw.xe66";
449 target-module@40d01000 {
450 compatible = "ti,sysc-omap2", "ti,sysc";
454 reg-names = "rev", "sysc", "syss";
455 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
458 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
462 clock-names = "fck";
464 reset-names = "rstctrl";
466 #size-cells = <1>;
467 #address-cells = <1>;
469 mmu0_dsp1: mmu@0 {
470 compatible = "ti,dra7-dsp-iommu";
473 #iommu-cells = <0>;
474 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
478 target-module@40d02000 {
479 compatible = "ti,sysc-omap2", "ti,sysc";
483 reg-names = "rev", "sysc", "syss";
484 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
487 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
491 clock-names = "fck";
493 reset-names = "rstctrl";
495 #size-cells = <1>;
496 #address-cells = <1>;
498 mmu1_dsp1: mmu@0 {
499 compatible = "ti,dra7-dsp-iommu";
502 #iommu-cells = <0>;
503 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
507 target-module@58882000 {
508 compatible = "ti,sysc-omap2", "ti,sysc";
512 reg-names = "rev", "sysc", "syss";
513 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
516 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
520 clock-names = "fck";
522 reset-names = "rstctrl";
523 #address-cells = <1>;
524 #size-cells = <1>;
527 mmu_ipu1: mmu@0 {
528 compatible = "ti,dra7-iommu";
531 #iommu-cells = <0>;
532 ti,iommu-bus-err-back;
536 target-module@55082000 {
537 compatible = "ti,sysc-omap2", "ti,sysc";
541 reg-names = "rev", "sysc", "syss";
542 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
545 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
549 clock-names = "fck";
551 reset-names = "rstctrl";
552 #address-cells = <1>;
553 #size-cells = <1>;
556 mmu_ipu2: mmu@0 {
557 compatible = "ti,dra7-iommu";
560 #iommu-cells = <0>;
561 ti,iommu-bus-err-back;
565 abb_mpu: regulator-abb-mpu {
566 compatible = "ti,abb-v3";
567 regulator-name = "abb_mpu";
568 #address-cells = <0>;
569 #size-cells = <0>;
571 ti,settling-time = <50>;
572 ti,clock-cycles = <16>;
577 reg-names = "setup-address", "control-address",
578 "int-address", "efuse-address",
579 "ldo-address";
580 ti,tranxdone-status-mask = <0x80>;
582 ti,ldovbb-override-mask = <0x400>;
584 ti,ldovbb-vset-mask = <0x1F>;
598 abb_ivahd: regulator-abb-ivahd {
599 compatible = "ti,abb-v3";
600 regulator-name = "abb_ivahd";
601 #address-cells = <0>;
602 #size-cells = <0>;
604 ti,settling-time = <50>;
605 ti,clock-cycles = <16>;
610 reg-names = "setup-address", "control-address",
611 "int-address", "efuse-address",
612 "ldo-address";
613 ti,tranxdone-status-mask = <0x40000000>;
615 ti,ldovbb-override-mask = <0x400>;
617 ti,ldovbb-vset-mask = <0x1F>;
631 abb_dspeve: regulator-abb-dspeve {
632 compatible = "ti,abb-v3";
633 regulator-name = "abb_dspeve";
634 #address-cells = <0>;
635 #size-cells = <0>;
637 ti,settling-time = <50>;
638 ti,clock-cycles = <16>;
643 reg-names = "setup-address", "control-address",
644 "int-address", "efuse-address",
645 "ldo-address";
646 ti,tranxdone-status-mask = <0x20000000>;
648 ti,ldovbb-override-mask = <0x400>;
650 ti,ldovbb-vset-mask = <0x1F>;
664 abb_gpu: regulator-abb-gpu {
665 compatible = "ti,abb-v3";
666 regulator-name = "abb_gpu";
667 #address-cells = <0>;
668 #size-cells = <0>;
670 ti,settling-time = <50>;
671 ti,clock-cycles = <16>;
676 reg-names = "setup-address", "control-address",
677 "int-address", "efuse-address",
678 "ldo-address";
679 ti,tranxdone-status-mask = <0x10000000>;
681 ti,ldovbb-override-mask = <0x400>;
683 ti,ldovbb-vset-mask = <0x1F>;
698 compatible = "ti,dra7xxx-qspi";
701 reg-names = "qspi_base", "qspi_mmap";
702 syscon-chipselects = <&scm_conf 0x558>;
703 #address-cells = <1>;
704 #size-cells = <0>;
707 clock-names = "fck";
708 num-cs = <4>;
715 compatible = "snps,dwc-ahci";
719 phy-names = "sata-phy";
722 ports-implemented = <0x1>;
728 compatible = "ti,am3352-gpmc";
733 dma-names = "rxtx";
734 gpmc,num-cs = <8>;
735 gpmc,num-waitpins = <2>;
736 #address-cells = <2>;
737 #size-cells = <1>;
738 interrupt-controller;
739 #interrupt-cells = <2>;
740 gpio-controller;
741 #gpio-cells = <2>;
745 target-module@56000000 {
746 compatible = "ti,sysc-omap4", "ti,sysc";
749 reg-names = "rev", "sysc";
750 ti,sysc-midle = <SYSC_IDLE_FORCE>,
753 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
757 clock-names = "fck";
758 #address-cells = <1>;
759 #size-cells = <1>;
764 compatible = "ti,irq-crossbar";
766 interrupt-controller;
767 interrupt-parent = <&wakeupgen>;
768 #interrupt-cells = <3>;
769 ti,max-irqs = <160>;
770 ti,max-crossbar-sources = <MAX_SOURCES>;
771 ti,reg-size = <2>;
772 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
773 ti,irqs-skip = <10 133 139 140>;
774 ti,irqs-safe-map = <0>;
777 target-module@58000000 {
778 compatible = "ti,sysc-omap2", "ti,sysc";
781 reg-names = "rev", "syss";
782 ti,syss-mask = <1>;
787 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
788 #address-cells = <1>;
789 #size-cells = <1>;
793 compatible = "ti,dra7-dss";
798 syscon-pll-ctrl = <&scm_conf 0x538>;
799 #address-cells = <1>;
800 #size-cells = <1>;
803 target-module@1000 {
804 compatible = "ti,sysc-omap2", "ti,sysc";
808 reg-names = "rev", "sysc", "syss";
809 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
812 ti,sysc-midle = <SYSC_IDLE_FORCE>,
815 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
819 ti,syss-mask = <1>;
821 clock-names = "fck";
822 #address-cells = <1>;
823 #size-cells = <1>;
827 compatible = "ti,dra7-dispc";
831 clock-names = "fck";
833 syscon-pol = <&scm_conf 0x534>;
837 target-module@40000 {
838 compatible = "ti,sysc-omap4", "ti,sysc";
841 reg-names = "rev", "sysc";
842 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
846 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
849 clock-names = "fck", "dss_clk";
850 #address-cells = <1>;
851 #size-cells = <1>;
855 compatible = "ti,dra7-hdmi";
860 reg-names = "wp", "pll", "phy", "core";
865 clock-names = "fck", "sys_clk";
867 dma-names = "audio_tx";
873 aes1_target: target-module@4b500000 {
874 compatible = "ti,sysc-omap2", "ti,sysc";
878 reg-names = "rev", "sysc", "syss";
879 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
881 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
885 ti,syss-mask = <1>;
888 clock-names = "fck";
889 #address-cells = <1>;
890 #size-cells = <1>;
894 compatible = "ti,omap4-aes";
898 dma-names = "tx", "rx";
900 clock-names = "fck";
904 aes2_target: target-module@4b700000 {
905 compatible = "ti,sysc-omap2", "ti,sysc";
909 reg-names = "rev", "sysc", "syss";
910 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
912 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
916 ti,syss-mask = <1>;
919 clock-names = "fck";
920 #address-cells = <1>;
921 #size-cells = <1>;
925 compatible = "ti,omap4-aes";
929 dma-names = "tx", "rx";
931 clock-names = "fck";
935 sham_target: target-module@4b101000 {
936 compatible = "ti,sysc-omap3-sham", "ti,sysc";
940 reg-names = "rev", "sysc", "syss";
941 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
943 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
946 ti,syss-mask = <1>;
949 clock-names = "fck";
950 #address-cells = <1>;
951 #size-cells = <1>;
955 compatible = "ti,omap5-sham";
959 dma-names = "rx";
961 clock-names = "fck";
965 opp_supply_mpu: opp-supply@4a003b20 {
966 compatible = "ti,omap5-opp-supply";
968 ti,efuse-settings = <
974 ti,absolute-max-voltage-uv = <1500000>;
979 thermal_zones: thermal-zones {
980 #include "omap4-cpu-thermal.dtsi"
981 #include "omap5-gpu-thermal.dtsi"
982 #include "omap5-core-thermal.dtsi"
983 #include "dra7-dspeve-thermal.dtsi"
984 #include "dra7-iva-thermal.dtsi"
990 polling-delay = <500>; /* milliseconds */
1030 #include "dra7-l4.dtsi"
1031 #include "dra7xx-clocks.dtsi"
1035 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1037 #reset-cells = <1>;
1040 prm_ipu: prm@500 {
1041 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1043 #reset-cells = <1>;
1047 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1049 #reset-cells = <1>;
1053 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1058 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1060 #reset-cells = <1>;
1064 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1069 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1074 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1079 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1084 /* Preferred always-on timer for clockevent */
1086 ti,no-reset-on-init;
1087 ti,no-idle;
1089 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
1090 assigned-clock-parents = <&sys_32k_ck>;