Lines Matching +full:0 +full:x19000000
24 ranges = <0x00000000 0x18000000 0x00001000>;
30 reg = <0x0300 0x100>;
38 reg = <0x0400 0x100>;
42 pinctrl-0 = <&pinmux_uart1>;
49 ranges = <0x00000000 0x19000000 0x00023000>;
53 a9pll: arm_clk@0 {
54 #clock-cells = <0>;
57 reg = <0x00000 0x1000>;
62 reg = <0x20000 0x100>;
67 reg = <0x20200 0x100>;
74 reg = <0x20600 0x20>;
82 reg = <0x20620 0x20>;
91 #address-cells = <0>;
93 reg = <0x21000 0x1000>,
94 <0x20100 0x100>;
99 reg = <0x22000 0x1000>;
121 #clock-cells = <0>;
127 #clock-cells = <0>;
135 #clock-cells = <0>;
143 #clock-cells = <0>;
153 reg = <0x1800c000 0x1000>;
155 #phy-cells = <0>;
162 reg = <0x18000000 0x1000>;
163 ranges = <0x00000000 0x18000000 0x00100000>;
168 interrupt-map-mask = <0x000fffff 0xffff>;
171 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
174 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
175 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
176 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
177 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
178 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
179 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
180 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
181 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
182 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
183 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
184 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
185 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
186 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
188 /* PCIe Controller 0 */
189 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
190 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
191 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
192 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
193 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
194 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
197 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
198 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
199 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
200 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
201 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
202 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
205 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
206 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
207 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
208 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
209 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
210 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
213 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
216 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
218 /* Ethernet Controller 0 */
219 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
222 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
225 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
228 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
231 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
232 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
233 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
234 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
235 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
236 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
237 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
238 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
240 chipcommon: chipcommon@0 {
241 reg = <0x00000000 0x1000>;
248 reg = <0x00012000 0x1000>;
252 reg = <0x00013000 0x1000>;
256 reg = <0x00014000 0x1000>;
260 reg = <0x00021000 0x1000>;
269 #usb-cells = <0>;
272 reg = <0x00021000 0x1000>;
277 #size-cells = <0>;
281 #trigger-source-cells = <0>;
286 #trigger-source-cells = <0>;
291 #usb-cells = <0>;
294 reg = <0x00022000 0x1000>;
298 #size-cells = <0>;
302 #trigger-source-cells = <0>;
307 #trigger-source-cells = <0>;
313 reg = <0x00023000 0x1000>;
322 #usb-cells = <0>;
325 reg = <0x00023000 0x1000>;
331 #size-cells = <0>;
335 #trigger-source-cells = <0>;
341 reg = <0x24000 0x800>;
345 reg = <0x25000 0x800>;
349 reg = <0x26000 0x800>;
353 reg = <0x27000 0x800>;
359 reg = <0x18002000 0x28>;
367 reg = <0x18003000 0x8>;
368 #size-cells = <0>;
376 #size-cells = <0>;
377 reg = <0x18003000 0x4>;
378 mux-mask = <0x200>;
380 mdio@0 {
381 reg = <0x0>;
383 #size-cells = <0>;
387 reg = <0x10>;
389 #phy-cells = <0>;
396 reg = <0x18105000 0x1000>;
401 reg = <0x18008000 0x20>;
410 reg = <0x18009000 0x50>;
413 #size-cells = <0>;
420 ranges = <0 0x1800c000 0x1000>;
426 reg = <0x100 0x1a4>;
433 reg = <0x1c0 0x24>;
463 reg = <0x1800c100 0x14>;
472 reg = <0x1800c140 0x24>;
481 reg = <0x1800c2c0 0x10>;
482 #thermal-sensor-cells = <0>;
487 reg = <0x18007000 0x1000>;
496 reg = <0x18004000 0x14>;
501 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
506 #size-cells = <0>;
513 reg = <0x18029200 0x184>,
514 <0x18029000 0x124>,
515 <0x1811b408 0x004>,
516 <0x180293a0 0x01c>;
536 #size-cells = <0>;
538 spi_nor: spi-nor@0 {
540 reg = <0>;
552 polling-delay-passive = <0>;
560 hysteresis = <0>;