Lines Matching +full:0 +full:x7ef01f00
21 #clock-cells = <0>;
28 #clock-cells = <0>;
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
53 reg = <0x40000000 0x100>;
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
63 <0x40046000 0x2000>;
71 reg = <0x7d5d2000 0xf00>;
75 #thermal-sensor-cells = <0>;
81 reg = <0x7e007000 0xb00>;
106 brcm,dma-channel-mask = <0x07f5>;
113 reg = <0x7e100000 0x114>,
114 <0x7e00a000 0x24>,
115 <0x7ec11000 0x20>;
126 reg = <0x7e104000 0x28>;
131 reg = <0x7e201400 0x200>;
136 arm,primecell-periphid = <0x00241011>;
142 reg = <0x7e201600 0x200>;
147 arm,primecell-periphid = <0x00241011>;
153 reg = <0x7e201800 0x200>;
158 arm,primecell-periphid = <0x00241011>;
164 reg = <0x7e201a00 0x200>;
169 arm,primecell-periphid = <0x00241011>;
175 reg = <0x7e204600 0x0200>;
179 #size-cells = <0>;
185 reg = <0x7e204800 0x0200>;
189 #size-cells = <0>;
195 reg = <0x7e204a00 0x0200>;
199 #size-cells = <0>;
205 reg = <0x7e204c00 0x0200>;
209 #size-cells = <0>;
215 reg = <0x7e205600 0x200>;
219 #size-cells = <0>;
225 reg = <0x7e205800 0x200>;
229 #size-cells = <0>;
235 reg = <0x7e205a00 0x200>;
239 #size-cells = <0>;
245 reg = <0x7e205c00 0x200>;
249 #size-cells = <0>;
255 reg = <0x7e206000 0x100>;
262 reg = <0x7e207000 0x100>;
269 reg = <0x7e20a000 0x100>;
276 reg = <0x7e20c800 0x28>;
286 reg = <0x7e216000 0x100>;
298 reg = <0x7ec12000 0x100>;
305 reg = <0x7ef00000 0x10>;
313 reg = <0x7ef00700 0x300>,
314 <0x7ef00300 0x200>,
315 <0x7ef00f00 0x80>,
316 <0x7ef00f80 0x80>,
317 <0x7ef01b00 0x200>,
318 <0x7ef01f00 0x400>,
319 <0x7ef00200 0x80>,
320 <0x7ef04300 0x100>,
321 <0x7ef20000 0x100>;
332 resets = <&dvp 0>;
341 reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
349 reg = <0x7ef05700 0x300>,
350 <0x7ef05300 0x200>,
351 <0x7ef05f00 0x80>,
352 <0x7ef05f80 0x80>,
353 <0x7ef06b00 0x200>,
354 <0x7ef06f00 0x400>,
355 <0x7ef00280 0x80>,
356 <0x7ef09300 0x100>,
357 <0x7ef20000 0x100>;
377 reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
395 ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
396 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
400 reg = <0x0 0x7e340000 0x100>;
432 #size-cells = <0>;
435 cpu0: cpu@0 {
438 reg = <0>;
440 cpu-release-addr = <0x0 0x000000d8>;
448 cpu-release-addr = <0x0 0x000000e0>;
456 cpu-release-addr = <0x0 0x000000e8>;
464 cpu-release-addr = <0x0 0x000000f0>;
473 ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
474 <0x6 0x00000000 0x6 0x00000000 0x40000000>;
478 reg = <0x0 0x7d500000 0x9310>;
486 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
487 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
492 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
493 0x0 0x04000000>;
499 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
500 0x0 0xc0000000>;
506 reg = <0x0 0x7d580000 0x10000>;
507 #address-cells = <0x1>;
508 #size-cells = <0x1>;
515 reg = <0xe14 0x8>;
517 #address-cells = <0x0>;
518 #size-cells = <0x1>;
1010 alloc-ranges = <0x0 0x00000000 0x40000000>;