Lines Matching +full:0 +full:x18020000

48 	memory@0 {
50 		reg = <0 0>;
55 		#size-cells = <0>;
57 		cpu@0 {
61 			reg = <0x0>;
74 		ranges = <0x00000000 0x19000000 0x1000000>;
80 			reg = <0x20200 0x100>;
88 			#address-cells = <0>;
90 			reg = <0x21000 0x1000>,
91 			      <0x20100 0x100>;
96 			reg = <0x22000 0x1000>;
110 			reg = <0x0301c800 0x2c>;
117 			reg = <0x0301d0a0 0x14>;
119 			#size-cells = <0>;
121 			pcie0_phy: phy@0 {
122 				reg = <0>;
123 				#phy-cells = <0>;
128 				#phy-cells = <0>;
134 			reg = <0x0301d0c8 0x30>,
135 			      <0x0301d24c 0x2c>;
155 			reg = <0x03024024 0x40>;
164 			reg = <0x03024800 0x50>,
165 			      <0x03024008 0x18>;
171 			interrupts = <0>;
176 			reg = <0x18002000 0x8>;
177 			#size-cells = <0>;
181 			gphy0: ethernet-phy@0 {
182 				reg = <0>;
192 			reg = <0x18007000 0x1000>;
197 				#size-cells = <0>;
199 				port@0 {
200 					reg = <0>;
225 			reg = <0x18008000 0x100>;
227 			#size-cells = <0>;
235 			reg = <0x18009000 0x1000>;
243 			reg = <0x1800a000 0x50>,
244 			      <0x0301d164 0x20>;
254 			reg = <0x1800b000 0x100>;
256 			#size-cells = <0>;
264 			reg = <0x18012000 0x1000>;
267 			interrupt-map-mask = <0 0 0 0>;
268 			interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
270 			linux,pci-domain = <0>;
272 			bus-range = <0x00 0xff>;
277 			ranges = <0x81000000 0 0	  0x28000000 0 0x00010000
278 				  0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
299 			reg = <0x18013000 0x1000>;
302 			interrupt-map-mask = <0 0 0 0>;
303 			interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
307 			bus-range = <0x00 0xff>;
312 			ranges = <0x81000000 0 0	  0x48000000 0 0x00010000
313 				  0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
334 			reg = <0x18018000 0x1000>;
351 			reg = <0x18020000 0x100>;
362 			reg = <0x18021000 0x100>;
373 			reg = <0x18022000 0x100>;
384 			reg = <0x18023000 0x100>;
395 			reg = <0x18028000 0x1000>;
397 			#size-cells = <0>;
399 			pinctrl-0 = <&spi_0>;
407 			reg = <0x18029000 0x1000>;
409 			#size-cells = <0>;
411 			pinctrl-0 = <&spi_1>;
419 			reg = <0x1802a000 0x1000>;
421 			#size-cells = <0>;
423 			pinctrl-0 = <&spi_2>;
431 			reg = <0x18032000 0x28>;
436 			reg = <0x18041000 0x100>;
446 			reg = <0x18042000 0x1000>,
447 			      <0x18110000 0x1000>;
455 			reg = <0x18043000 0x100>;
465 			reg = <0x18046000 0x600>, <0xf8105408 0x600>,
466 			      <0x18046f00 0x20>;
471 			#size-cells = <0>;
478 			reg = <0x18048000 0x100>;
485 			reg = <0x18048800 0x100>;
492 			reg = <0x180a0000 0x1000>;
502 			reg = <0x180a2000 0x1000>;
515 			reg = <0x180a5000 0x668>;
522 			gpio-ranges = <&pinctrl 0 42 1>,
577 			reg = <0x180a6000 0xc30>;
604 			reg = <0x180aa500 0xc4>;
612 			reg = <0x180ac000 0x14c>;
618 			col-debounce-filter-period = <0>;
619 			status-debounce-filter-period = <0>;