Lines Matching +full:0 +full:x16000000
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
46 #clock-cells = <0>;
52 #clock-cells = <0>;
60 interrupts = <0 29 4>, <0 82 4>;
67 ranges = <0x10000000 0x10000000 0xc0000000>;
73 reg = <0x10301000 0x1000>,
74 <0x10302000 0x0100>;
79 reg = <0x10E30020 0x4>;
86 #sound-dai-cells = <0>;
88 reg = <0x10E30000 0x400>;
94 #sound-dai-cells = <0>;
96 reg = <0x10D01000 0x100>;
97 dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
105 ranges = <0x13240000 0x13240000 0x00010000>;
111 reg = <0x13240000 0x00010000>;
116 ns_m3_rproc@0 {
118 reg = <0x13240000 0x00010000>;
119 interrupts = <0 123 0>;
124 reg = <0x13240000 0x00010000>;
125 interrupts = <0 126 0>;
128 ns_kal_rproc@0 {
130 reg = <0x13240000 0x00010000>;
131 interrupts = <0 124 0>;
136 reg = <0x13240000 0x00010000>;
137 interrupts = <0 127 0>;
143 reg = <0x18880000 0x1000>,
144 <0x10E40000 0x1000>;
146 audio_ac97_pmx: audio_ac97@0 {
153 audio_func_dbg_pmx: audio_func_dbg@0 {
160 audio_i2s_pmx: audio_i2s@0 {
167 audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
174 audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
181 audio_uart0_pmx: audio_uart0@0 {
188 audio_uart1_pmx: audio_uart1@0 {
195 audio_uart2_pmx0: audio_uart2@0 {
209 c_can_trnsvr_pmx: c_can_trnsvr@0 {
216 c0_can_pmx0: c0_can@0 {
230 c1_can_pmx0: c1_can@0 {
251 ca_audio_lpc_pmx: ca_audio_lpc@0 {
258 ca_bt_lpc_pmx: ca_bt_lpc@0 {
265 ca_coex_pmx: ca_coex@0 {
272 ca_curator_lpc_pmx: ca_curator_lpc@0 {
279 ca_pcm_debug_pmx: ca_pcm_debug@0 {
286 ca_pio_pmx: ca_pio@0 {
293 ca_sdio_debug_pmx: ca_sdio_debug@0 {
300 ca_spi_pmx: ca_spi@0 {
307 ca_trb_pmx: ca_trb@0 {
314 ca_uart_debug_pmx: ca_uart_debug@0 {
321 clkc_pmx0: clkc@0 {
335 gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
342 gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
349 gn_gnss_uart_pmx: gn_gnss_uart@0 {
356 gn_trg_spi_pmx0: gn_trg_spi@0 {
370 cvbs_dbg_pmx: cvbs_dbg@0 {
377 cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
489 gn_gnss_power_pmx: gn_gnss_power@0 {
496 gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
503 gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
510 gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
517 gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
524 gn_gnss_tm_pmx: gn_gnss_tm@0 {
531 gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
538 gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
545 gn_trg_pmx0: gn_trg@0 {
559 gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
587 i2c0_pmx: i2c0@0 {
594 i2c1_pmx: i2c1@0 {
601 jtag_pmx0: jtag@0 {
608 ks_kas_spi_pmx0: ks_kas_spi@0 {
615 ld_ldd_pmx: ld_ldd@0 {
622 ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
629 ld_ldd_fck_pmx: ld_ldd_fck@0 {
636 ld_ldd_lck_pmx: ld_ldd_lck@0 {
643 lr_lcdrom_pmx: lr_lcdrom@0 {
650 lvds_analog_pmx: lvds_analog@0 {
657 nd_df_pmx: nd_df@0 {
664 nd_df_nowp_pmx: nd_df_nowp@0 {
671 ps_pmx: ps@0 {
678 pwc_core_on_pmx: pwc_core_on@0 {
685 pwc_ext_on_pmx: pwc_ext_on@0 {
692 pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
699 pwc_io_on_pmx: pwc_io_on@0 {
706 pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
713 pwc_mem_on_pmx: pwc_mem_on@0 {
720 pwc_on_key_b_pmx0: pwc_on_key_b@0 {
727 pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
734 pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
741 pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
748 pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
755 pw_cko0_pmx0: pw_cko0@0 {
776 pw_cko1_pmx0: pw_cko1@0 {
790 pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
804 pw_pwm0_pmx: pw_pwm0@0 {
811 pw_pwm1_pmx: pw_pwm1@0 {
818 pw_pwm2_pmx0: pw_pwm2@0 {
832 pw_pwm3_pmx0: pw_pwm3@0 {
846 pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
860 pw_backlight_pmx0: pw_backlight@0 {
874 rg_eth_mac_pmx: rg_eth_mac@0 {
881 rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
888 rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
895 rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
913 sd0_pmx: sd0@0 {
920 sd0_4bit_pmx: sd0_4bit@0 {
927 sd1_pmx: sd1@0 {
934 sd1_4bit_pmx0: sd1_4bit@0 {
948 sd2_pmx0: sd2@0 {
955 sd2_no_cdb_pmx0: sd2_no_cdb@0 {
962 sd3_pmx: sd3@0 {
969 sd5_pmx: sd5@0 {
976 sd6_pmx0: sd6@0 {
990 sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
997 sp0_qspi_pmx: sp0_qspi@0 {
1004 sp1_spi_pmx: sp1_spi@0 {
1011 tpiu_trace_pmx: tpiu_trace@0 {
1018 uart0_pmx: uart0@0 {
1025 uart0_nopause_pmx: uart0_nopause@0 {
1032 uart1_pmx: uart1@0 {
1039 uart2_pmx: uart2@0 {
1046 uart3_pmx0: uart3@0 {
1074 uart3_nopause_pmx0: uart3_nopause@0 {
1088 uart4_pmx0: uart4@0 {
1109 uart4_nopause_pmx: uart4_nopause@0 {
1116 usb0_drvvbus_pmx: usb0_drvvbus@0 {
1123 usb1_drvvbus_pmx: usb1_drvvbus@0 {
1130 visbus_dout_pmx: visbus_dout@0 {
1137 vi_vip1_pmx: vi_vip1@0 {
1144 vi_vip1_ext_pmx: vi_vip1_ext@0 {
1151 vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1158 vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1170 ranges = <0x13240000 0x13240000 0x00010000>;
1171 pmipc@0x13240000 {
1173 reg = <0x13240000 0x00010000>;
1181 ranges = <0x10830000 0x10830000 0x18000>;
1184 reg = <0x10830000 0x18000>;
1192 ranges = <0x10250000 0x10250000 0x3000>;
1195 reg = <0x10250000 0x3000>;
1203 ranges = <0x10200000 0x10200000 0x3000>;
1206 reg = <0x10200000 0x3000>;
1214 ranges = <0x18641000 0x18641000 0x3000>,
1215 <0x18620000 0x18620000 0x1000>,
1216 <0x18630000 0x18630000 0x10000>;
1220 reg = <0x18641000 0x3000>;
1225 reg = <0x18620000 0x1000>;
1232 reg = <0x18630000 0x10000>;
1244 ranges = <0x18000000 0x18000000 0x0000ffff>,
1245 <0x18010000 0x18010000 0x1000>,
1246 <0x18020000 0x18020000 0x1000>,
1247 <0x18030000 0x18030000 0x1000>,
1248 <0x18040000 0x18040000 0x1000>,
1249 <0x18050000 0x18050000 0x1000>,
1250 <0x18060000 0x18060000 0x1000>,
1251 <0x180b0000 0x180b0000 0x4000>,
1252 <0x18100000 0x18100000 0x3000>,
1253 <0x18250000 0x18250000 0x10000>,
1254 <0x18200000 0x18200000 0x1000>;
1257 cell-index = <0>;
1259 reg = <0x18000000 0x1000>;
1260 interrupts = <0 12 0>;
1266 gnssmfw@0x18100000 {
1268 reg = <0x18100000 0x3000>;
1272 cell-index = <0>;
1274 reg = <0x18010000 0x1000>;
1275 interrupts = <0 17 0>;
1285 reg = <0x18020000 0x1000>;
1286 interrupts = <0 18 0>;
1294 reg = <0x18030000 0x1000>;
1295 interrupts = <0 19 0>;
1305 reg = <0x18040000 0x1000>;
1306 interrupts = <0 66 0>;
1316 reg = <0x18050000 0x1000>;
1317 interrupts = <0 69 0>;
1320 dmas = <&dmac0 0>, <&dmac0 1>;
1327 reg = <0x18060000 0x1000>;
1328 interrupts = <0 71 0>;
1337 reg = <0x180b0000 0x4000>;
1338 interrupts = <0 59 0>, <0 70 0>;
1349 reg = <0x18250000 0x10000>;
1350 interrupts = <0 27 0>;
1355 reg = <0x18200000 0x1000>;
1356 interrupts = <0 16 0>;
1359 #size-cells = <0>;
1371 ranges = <0x13000000 0x13000000 0x3000>,
1372 <0x13010000 0x13010000 0x1400>,
1373 <0x13010800 0x13010800 0x100>,
1374 <0x13011000 0x13011000 0x100>;
1375 gpum@0x13000000 {
1377 reg = <0x13000000 0x3000>;
1382 reg = <0x13010800 0x100>;
1383 interrupts = <0 8 0>;
1391 reg = <0x13011000 0x100>;
1392 interrupts = <0 9 0>;
1397 sdr@0x13010000 {
1399 reg = <0x13010000 0x1400>;
1400 interrupts = <0 7 0>,
1401 <0 8 0>,
1402 <0 9 0>;
1404 dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
1413 ranges = <0x15000000 0x15000000 0x00600000>,
1414 <0x16000000 0x16000000 0x00200000>,
1415 <0x17000000 0x17000000 0x10000>,
1416 <0x17020000 0x17020000 0x1000>,
1417 <0x17030000 0x17030000 0x1000>,
1418 <0x17040000 0x17040000 0x1000>,
1419 <0x17050000 0x17050000 0x10000>,
1420 <0x17060000 0x17060000 0x200>,
1421 <0x17060200 0x17060200 0x100>,
1422 <0x17070000 0x17070000 0x200>,
1423 <0x17070200 0x17070200 0x100>,
1424 <0x170A0000 0x170A0000 0x3000>;
1428 reg = <0x15000000 0x10000>;
1429 interrupts = <0 5 0>;
1435 reg = <0x170A0000 0x3000>;
1442 reg = <0x17040000 0x1000>;
1443 interrupts = <0 13 0>, <0 14 0>;
1450 gpio-ranges = <&pinctrl 0 0 0>,
1451 <&pinctrl 32 0 0>;
1458 reg = <0x17050000 0x10000>;
1460 pinctrl-0 = <&nd_df_pmx>;
1461 interrupts = <0 41 0>;
1467 cell-index = <0>;
1469 reg = <0x16000000 0x100000>;
1470 interrupts = <0 38 0>;
1482 reg = <0x16100000 0x100000>;
1483 interrupts = <0 38 0>;
1493 reg = <0x17000000 0x10000>;
1494 interrupts = <0 72 0>,
1495 <0 73 0>;
1500 cell-index = <0>;
1502 reg = <0x17060000 0x200>;
1503 interrupts = <0 10 0>;
1515 reg = <0x17070000 0x200>;
1516 interrupts = <0 11 0>;
1525 usbphy0: usbphy@0 {
1527 reg = <0x17060200 0x100>;
1534 reg = <0x17070200 0x100>;
1540 cell-index = <0>;
1542 reg = <0x17020000 0x1000>;
1543 interrupts = <0 24 0>;
1546 #size-cells = <0>;
1555 ranges = <0x13290000 0x13290000 0x3000>,
1556 <0x13300000 0x13300000 0x1000>,
1557 <0x14200000 0x14200000 0x600000>;
1561 reg = <0x13290000 0x3000>;
1568 reg = <0x13300000 0x1000>;
1569 interrupts = <0 43 0>, <0 44 0>,
1570 <0 45 0>, <0 46 0>;
1577 gpio-ranges = <&pinctrl 0 0 0>,
1578 <&pinctrl 32 0 0>,
1579 <&pinctrl 64 0 0>,
1580 <&pinctrl 96 0 0>;
1590 reg = <0x14200000 0x100000>;
1591 interrupts = <0 23 0>;
1611 reg = <0x14300000 0x100000>;
1612 interrupts = <0 23 0>;
1622 reg = <0x14500000 0x100000>;
1623 interrupts = <0 39 0>;
1634 reg = <0x14600000 0x100000>;
1635 interrupts = <0 98 0>;
1645 reg = <0x14700000 0x100000>;
1646 interrupts = <0 98 0>;
1658 ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1659 <0x10d60000 0x10d60000 0x0000ffff>,
1660 <0x10d80000 0x10d80000 0x0000ffff>,
1661 <0x10d90000 0x10d90000 0x0000ffff>,
1662 <0x10ED0000 0x10ED0000 0x3000>,
1663 <0x10dc8000 0x10dc8000 0x1000>,
1664 <0x10dc0000 0x10dc0000 0x1000>,
1665 <0x10db0000 0x10db0000 0x4000>,
1666 <0x10d40000 0x10d40000 0x1000>,
1667 <0x10d30000 0x10d30000 0x1000>;
1671 reg = <0x10dc0000 0x1000>;
1672 interrupts = <0 0 0>,
1673 <0 1 0>,
1674 <0 2 0>,
1675 <0 49 0>,
1676 <0 50 0>,
1677 <0 51 0>;
1683 reg = <0x10dc8000 0x1000>;
1684 interrupts = <0 74 0>,
1685 <0 75 0>,
1686 <0 76 0>,
1687 <0 77 0>,
1688 <0 78 0>,
1689 <0 79 0>;
1695 reg = <0x10db0000 0x2000>;
1696 interrupts = <0 85 0>;
1697 sirf,vip_cma_size = <0xC00000>;
1702 reg = <0x10db2000 0x2000>;
1709 reg = <0x10d50000 0xffff>;
1710 interrupts = <0 55 0>;
1719 reg = <0x10d60000 0xffff>;
1720 interrupts = <0 56 0>;
1728 reg = <0x10d80000 0xffff>;
1729 interrupts = <0 34 0>;
1736 reg = <0x10d90000 0xffff>;
1737 interrupts = <0 42 0>;
1743 reg = <0x10ED0000 0x3000>;
1744 interrupts = <0 102 0>;
1749 reg = <0x10d30000 0x1000>;
1758 reg = <0x10d40000 0x1000>;
1759 interrupts = <0 22 0>;
1764 #size-cells = <0>;
1773 ranges = <0x10820000 0x10820000 0x3000>,
1774 <0x10800000 0x10800000 0x2000>;
1777 reg = <0x10820000 0x3000>;
1778 interrupts = <0 105 0>;
1781 memory-controller@0x10800000 {
1783 reg = <0x10800000 0x2000>;
1792 ranges = <0x11002000 0x11002000 0x0000ffff>,
1793 <0x11010000 0x11010000 0x3000>,
1794 <0x11000000 0x11000000 0x1000>,
1795 <0x11001000 0x11001000 0x1000>;
1800 reg = <0x11002000 0x1000>;
1801 interrupts = <0 99 0>;
1810 reg = <0x11000000 0x1000>;
1811 interrupts = <0 100 0>;
1824 reg = <0x11001000 0x1000>;
1830 dmas = <&dmac4 0>, <&dmac4 1>;
1836 reg = <0x11010000 0x3000>;
1844 ranges = <0x18810000 0x18810000 0x3000>,
1845 <0x18840000 0x18840000 0x1000>,
1846 <0x18890000 0x18890000 0x1000>,
1847 <0x188B0000 0x188B0000 0x10000>,
1848 <0x188D0000 0x188D0000 0x1000>;
1851 reg = <0x18810000 0x3000>;
1852 interrupts = <0 109 0>;
1859 reg = <0x18890000 0x1000>;
1860 interrupts = <0 47 0>;
1865 gpio-ranges = <&pinctrl 0 0 0>;
1875 reg = <0x18840000 0x1000>;
1879 reg = <0x2000 0x100>;
1880 interrupts = <0 52 0>;
1884 reg = <0x3000 0x100>;
1889 cell-index = <0>;
1891 reg = <0x188B0000 0x10000>;
1892 interrupts = <0 15 0>;
1894 #size-cells = <0>;
1897 retain@0x188D0000 {
1899 reg = <0x188D0000 0x1000>;
1908 ranges = <0x13100000 0x13100000 0x20000>,
1909 <0x10e10000 0x10e10000 0x10000>,
1910 <0x17010000 0x17010000 0x10000>;
1914 reg = <0x13100000 0x10000>;
1915 interrupts = <0 30 0>;
1920 reg = <0x13110000 0x10000>;
1921 interrupts = <0 31 0>;
1927 reg = <0x10e10000 0x10000>;
1928 interrupts = <0 64 0>;
1934 reg = <0x17010000 0x10000>;
1935 interrupts = <0 61 0>;
1945 ranges = <0x12000000 0x12000000 0x1000000>;
1949 reg = <0x12000000 0x1000000>;
1950 interrupts = <0 6 0>;