Lines Matching +full:0 +full:x10000000
37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x08000000>;
54 #clock-cells = <0>;
55 clock-frequency = <0>;
60 #clock-cells = <0>;
61 clock-frequency = <0>;
67 reg = <0x00300000 0x28000>;
70 ranges = <0 0x00300000 0x28000>;
81 reg = <0x00500000 0x100000>;
90 reg = <0x00600000 0x1000>;
93 pinctrl-0 = <&pinctrl_fb>;
105 reg = <0x10000000 0x80000000>;
106 ranges = <0x0 0x0 0x10000000 0x10000000
107 0x1 0x0 0x20000000 0x10000000
108 0x2 0x0 0x30000000 0x10000000
109 0x3 0x0 0x40000000 0x10000000
110 0x4 0x0 0x50000000 0x10000000
111 0x5 0x0 0x60000000 0x10000000
112 0x6 0x0 0x70000000 0x10000000
113 0x7 0x0 0x80000000 0x10000000>;
135 #size-cells = <0>;
136 reg = <0xfffa0000 0x100>;
137 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
138 <18 IRQ_TYPE_LEVEL_HIGH 0>,
139 <19 IRQ_TYPE_LEVEL_HIGH 0>;
146 reg = <0xfffa4000 0x4000>;
156 reg = <0xfffa8000 0x600>;
157 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
159 pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
161 #size-cells = <0>;
170 pinctrl-0 = <&pinctrl_i2c_twi>;
171 reg = <0xfffac000 0x100>;
174 #size-cells = <0>;
181 reg = <0xfffb0000 0x200>;
186 pinctrl-0 = <&pinctrl_usart0>;
194 reg = <0xfffb4000 0x200>;
199 pinctrl-0 = <&pinctrl_usart1>;
207 reg = <0xfffb8000 0x200>;
212 pinctrl-0 = <&pinctrl_usart2>;
220 reg = <0xfffbc000 0x4000>;
223 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
231 reg = <0xfffc0000 0x4000>;
234 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
242 reg = <0xfffc4000 0x4000>;
245 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
253 #size-cells = <0>;
255 reg = <0xfffc8000 0x200>;
256 cs-gpios = <0>, <0>, <0>, <0>;
259 pinctrl-0 = <&pinctrl_spi0>;
267 #size-cells = <0>;
269 reg = <0xfffcc000 0x200>;
272 pinctrl-0 = <&pinctrl_spi1>;
280 reg = <0xffffea00 0x200>;
285 reg = <0xffffec00 0x200>;
290 reg = <0xffffee00 0x200>;
297 reg = <0xfffff000 0x200>;
303 reg = <0xfffff200 0x200>;
306 pinctrl-0 = <&pinctrl_dbgu>;
316 ranges = <0xfffff400 0xfffff400 0x600>;
320 <0xffffffff 0xfffffff7>, /* pioA */
321 <0xffffffff 0xfffffff4>, /* pioB */
322 <0xffffffff 0xffffff07>; /* pioC */
326 pinctrl_dbgu: dbgu-0 {
334 pinctrl_usart0: usart0-0 {
340 pinctrl_usart0_rts: usart0_rts-0 {
345 pinctrl_usart0_cts: usart0_cts-0 {
352 pinctrl_usart1: usart1-0 {
358 pinctrl_usart1_rts: usart1_rts-0 {
363 pinctrl_usart1_cts: usart1_cts-0 {
370 pinctrl_usart2: usart2-0 {
376 pinctrl_usart2_rts: usart2_rts-0 {
381 pinctrl_usart2_cts: usart2_cts-0 {
388 pinctrl_nand_rb: nand-rb-0 {
393 pinctrl_nand_cs: nand-cs-0 {
400 pinctrl_mmc0_clk: mmc0_clk-0 {
405 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
408 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
411 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
420 pinctrl_ssc0_tx: ssc0_tx-0 {
427 pinctrl_ssc0_rx: ssc0_rx-0 {
436 pinctrl_ssc1_tx: ssc1_tx-0 {
443 pinctrl_ssc1_rx: ssc1_rx-0 {
452 pinctrl_ssc2_tx: ssc2_tx-0 {
459 pinctrl_ssc2_rx: ssc2_rx-0 {
468 pinctrl_spi0: spi0-0 {
470 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
477 pinctrl_spi1: spi1-0 {
486 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
490 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
494 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
498 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
502 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
506 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
510 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
514 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
518 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
524 pinctrl_i2c_bitbang: i2c-0-bitbang {
529 pinctrl_i2c_twi: i2c-0-twi {
537 pinctrl_fb: fb-0 {
565 reg = <0xfffff400 0x200>;
576 reg = <0xfffff600 0x200>;
587 reg = <0xfffff800 0x200>;
599 reg = <0xfffffc00 0x100>;
608 reg = <0xfffffd00 0x10>;
614 reg = <0xfffffd10 0x10>;
620 reg = <0xfffffd30 0xf>;
627 reg = <0xfffffd20 0x10>;
635 reg = <0xfffffd40 0x10>;
643 reg = <0xfffffd50 0x10>;
649 i2c-gpio-0 {
652 pinctrl-0 = <&pinctrl_i2c_bitbang>;
659 #size-cells = <0>;