Lines Matching +full:0 +full:xf0
28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
86 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
87 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
88 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
89 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
90 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
91 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
92 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
93 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
94 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
95 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
96 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
97 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
98 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
99 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
101 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
102 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
103 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
104 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
105 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
106 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
107 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
108 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
110 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
111 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
113 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
114 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
116 pcie1: pcie@1,0 {
118 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
119 reg = <0x0800 0 0 0 0>;
123 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
124 0x81000000 0 0 0x81000000 0x1 0 1 0>;
125 bus-range = <0x00 0xff>;
126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 58>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <0>;
134 pcie2: pcie@2,0 {
136 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
137 reg = <0x1000 0 0 0 0>;
141 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
142 0x81000000 0 0 0x81000000 0x2 0 1 0>;
143 bus-range = <0x00 0xff>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 59>;
146 marvell,pcie-port = <0>;
152 pcie3: pcie@3,0 {
154 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
155 reg = <0x1800 0 0 0 0>;
159 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
160 0x81000000 0 0 0x81000000 0x3 0 1 0>;
161 bus-range = <0x00 0xff>;
162 interrupt-map-mask = <0 0 0 0>;
163 interrupt-map = <0 0 0 0 &mpic 60>;
164 marvell,pcie-port = <0>;
170 pcie4: pcie@4,0 {
172 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
173 reg = <0x2000 0 0 0 0>;
177 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
178 0x81000000 0 0 0x81000000 0x4 0 1 0>;
179 bus-range = <0x00 0xff>;
180 interrupt-map-mask = <0 0 0 0>;
181 interrupt-map = <0 0 0 0 &mpic 61>;
182 marvell,pcie-port = <0>;
188 pcie5: pcie@5,0 {
190 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
191 reg = <0x2800 0 0 0 0>;
195 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
196 0x81000000 0 0 0x81000000 0x5 0 1 0>;
197 bus-range = <0x00 0xff>;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 62>;
201 marvell,pcie-lane = <0>;
206 pcie6: pcie@6,0 {
208 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
209 reg = <0x3000 0 0 0 0>;
213 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
214 0x81000000 0 0 0x81000000 0x6 0 1 0>;
215 bus-range = <0x00 0xff>;
216 interrupt-map-mask = <0 0 0 0>;
217 interrupt-map = <0 0 0 0 &mpic 63>;
224 pcie7: pcie@7,0 {
226 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
227 reg = <0x3800 0 0 0 0>;
231 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
232 0x81000000 0 0 0x81000000 0x7 0 1 0>;
233 bus-range = <0x00 0xff>;
234 interrupt-map-mask = <0 0 0 0>;
235 interrupt-map = <0 0 0 0 &mpic 64>;
242 pcie8: pcie@8,0 {
244 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
245 reg = <0x4000 0 0 0 0>;
249 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
250 0x81000000 0 0 0x81000000 0x8 0 1 0>;
251 bus-range = <0x00 0xff>;
252 interrupt-map-mask = <0 0 0 0>;
253 interrupt-map = <0 0 0 0 &mpic 65>;
260 pcie9: pcie@9,0 {
262 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
263 reg = <0x4800 0 0 0 0>;
267 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
268 0x81000000 0 0 0x81000000 0x9 0 1 0>;
269 bus-range = <0x00 0xff>;
270 interrupt-map-mask = <0 0 0 0>;
271 interrupt-map = <0 0 0 0 &mpic 99>;
273 marvell,pcie-lane = <0>;
278 pcie10: pcie@a,0 {
280 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
281 reg = <0x5000 0 0 0 0>;
285 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
286 0x81000000 0 0 0x81000000 0xa 0 1 0>;
287 bus-range = <0x00 0xff>;
288 interrupt-map-mask = <0 0 0 0>;
289 interrupt-map = <0 0 0 0 &mpic 103>;
291 marvell,pcie-lane = <0>;
301 reg = <0x18100 0x40>, <0x181c0 0x08>;
310 clocks = <&coreclk 0>;
316 reg = <0x18140 0x40>, <0x181c8 0x08>;
325 clocks = <&coreclk 0>;
331 reg = <0x18180 0x40>;
342 reg = <0x34000 0x4000>;