Lines Matching +full:3 +full:- +full:port
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
43 clock-latency = <1000000>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
54 compatible = "marvell,armada-xp-pcie";
58 #address-cells = <3>;
59 #size-cells = <2>;
61 msi-parent = <&mpic>;
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
99 #address-cells = <3>;
100 #size-cells = <2>;
101 #interrupt-cells = <1>;
104 bus-range = <0x00 0xff>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 58>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
122 bus-range = <0x00 0xff>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 59>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <1>;
131 pcie3: pcie@3,0 {
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
140 bus-range = <0x00 0xff>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &mpic 60>;
143 marvell,pcie-port = <0>;
144 marvell,pcie-lane = <2>;
151 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
153 #address-cells = <3>;
154 #size-cells = <2>;
155 #interrupt-cells = <1>;
158 bus-range = <0x00 0xff>;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
162 marvell,pcie-lane = <3>;
169 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
171 #address-cells = <3>;
172 #size-cells = <2>;
173 #interrupt-cells = <1>;
176 bus-range = <0x00 0xff>;
177 interrupt-map-mask = <0 0 0 0>;
178 interrupt-map = <0 0 0 0 &mpic 62>;
179 marvell,pcie-port = <1>;
180 marvell,pcie-lane = <0>;
187 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
189 #address-cells = <3>;
190 #size-cells = <2>;
191 #interrupt-cells = <1>;
194 bus-range = <0x00 0xff>;
195 interrupt-map-mask = <0 0 0 0>;
196 interrupt-map = <0 0 0 0 &mpic 63>;
197 marvell,pcie-port = <1>;
198 marvell,pcie-lane = <1>;
205 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
207 #address-cells = <3>;
208 #size-cells = <2>;
209 #interrupt-cells = <1>;
212 bus-range = <0x00 0xff>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 64>;
215 marvell,pcie-port = <1>;
216 marvell,pcie-lane = <2>;
223 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
225 #address-cells = <3>;
226 #size-cells = <2>;
227 #interrupt-cells = <1>;
230 bus-range = <0x00 0xff>;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 65>;
233 marvell,pcie-port = <1>;
234 marvell,pcie-lane = <3>;
241 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
243 #address-cells = <3>;
244 #size-cells = <2>;
245 #interrupt-cells = <1>;
248 bus-range = <0x00 0xff>;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &mpic 99>;
251 marvell,pcie-port = <2>;
252 marvell,pcie-lane = <0>;
258 internal-regs {
260 compatible = "marvell,armada-370-gpio",
261 "marvell,orion-gpio";
263 reg-names = "gpio", "pwm";
265 gpio-controller;
266 #gpio-cells = <2>;
267 #pwm-cells = <2>;
268 interrupt-controller;
269 #interrupt-cells = <2>;
275 compatible = "marvell,armada-370-gpio",
276 "marvell,orion-gpio";
278 reg-names = "gpio", "pwm";
280 gpio-controller;
281 #gpio-cells = <2>;
282 #pwm-cells = <2>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
290 compatible = "marvell,armada-370-gpio",
291 "marvell,orion-gpio";
293 ngpios = <3>;
294 gpio-controller;
295 #gpio-cells = <2>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
302 compatible = "marvell,armada-xp-neta";
313 compatible = "marvell,mv78260-pinctrl";