Lines Matching +full:0 +full:xf0
27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
69 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
70 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
71 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
72 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
73 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
74 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
75 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
76 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
77 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
78 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
79 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
80 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
81 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
83 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
84 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
85 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
86 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
87 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
88 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
89 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
90 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
92 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
93 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
95 pcie1: pcie@1,0 {
97 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
98 reg = <0x0800 0 0 0 0>;
102 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
103 0x81000000 0 0 0x81000000 0x1 0 1 0>;
104 bus-range = <0x00 0xff>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 58>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <0>;
113 pcie2: pcie@2,0 {
115 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
116 reg = <0x1000 0 0 0 0>;
120 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
121 0x81000000 0 0 0x81000000 0x2 0 1 0>;
122 bus-range = <0x00 0xff>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 59>;
125 marvell,pcie-port = <0>;
131 pcie3: pcie@3,0 {
133 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
134 reg = <0x1800 0 0 0 0>;
138 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
139 0x81000000 0 0 0x81000000 0x3 0 1 0>;
140 bus-range = <0x00 0xff>;
141 interrupt-map-mask = <0 0 0 0>;
142 interrupt-map = <0 0 0 0 &mpic 60>;
143 marvell,pcie-port = <0>;
149 pcie4: pcie@4,0 {
151 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
152 reg = <0x2000 0 0 0 0>;
156 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
157 0x81000000 0 0 0x81000000 0x4 0 1 0>;
158 bus-range = <0x00 0xff>;
159 interrupt-map-mask = <0 0 0 0>;
160 interrupt-map = <0 0 0 0 &mpic 61>;
161 marvell,pcie-port = <0>;
167 pcie5: pcie@5,0 {
169 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
170 reg = <0x2800 0 0 0 0>;
174 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
175 0x81000000 0 0 0x81000000 0x5 0 1 0>;
176 bus-range = <0x00 0xff>;
177 interrupt-map-mask = <0 0 0 0>;
178 interrupt-map = <0 0 0 0 &mpic 62>;
180 marvell,pcie-lane = <0>;
185 pcie6: pcie@6,0 {
187 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
188 reg = <0x3000 0 0 0 0>;
192 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
193 0x81000000 0 0 0x81000000 0x6 0 1 0>;
194 bus-range = <0x00 0xff>;
195 interrupt-map-mask = <0 0 0 0>;
196 interrupt-map = <0 0 0 0 &mpic 63>;
203 pcie7: pcie@7,0 {
205 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
206 reg = <0x3800 0 0 0 0>;
210 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
211 0x81000000 0 0 0x81000000 0x7 0 1 0>;
212 bus-range = <0x00 0xff>;
213 interrupt-map-mask = <0 0 0 0>;
214 interrupt-map = <0 0 0 0 &mpic 64>;
221 pcie8: pcie@8,0 {
223 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
224 reg = <0x4000 0 0 0 0>;
228 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
229 0x81000000 0 0 0x81000000 0x8 0 1 0>;
230 bus-range = <0x00 0xff>;
231 interrupt-map-mask = <0 0 0 0>;
232 interrupt-map = <0 0 0 0 &mpic 65>;
239 pcie9: pcie@9,0 {
241 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
242 reg = <0x4800 0 0 0 0>;
246 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
247 0x81000000 0 0 0x81000000 0x9 0 1 0>;
248 bus-range = <0x00 0xff>;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &mpic 99>;
252 marvell,pcie-lane = <0>;
262 reg = <0x18100 0x40>, <0x181c0 0x08>;
271 clocks = <&coreclk 0>;
277 reg = <0x18140 0x40>, <0x181c8 0x08>;
286 clocks = <&coreclk 0>;
292 reg = <0x18180 0x40>;
303 reg = <0x34000 0x4000>;