Lines Matching +full:0 +full:x100000
28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
55 * 98DX3236 has 1 x1 PCIe unit Gen2.0
66 bus-range = <0x00 0xff>;
69 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
70 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
71 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
73 pcie1: pcie@1,0 {
75 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
76 reg = <0x0800 0 0 0 0>;
80 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
81 0x81000000 0 0 0x81000000 0x1 0 1 0>;
82 bus-range = <0x00 0xff>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &mpic 58>;
85 marvell,pcie-port = <0>;
86 marvell,pcie-lane = <0>;
95 reg = <0x1400 0x500>;
100 reg = <0x08000 0x1000>;
101 cache-id-part = <0x100>;
109 reg = <0x18100 0x40>;
121 reg = <0x18140 0x40>;
127 reg = <0x18180 0x40>;
138 reg = <0x18200 0x500>;
143 reg = <0x18220 0x4>;
144 clocks = <&coreclk 0>;
151 reg = <0x18700 0x24>, <0x1c054 0x10>;
161 reg = <0x21000 0x8>;
174 reg = <0xf0800 0x100
175 0xf0a00 0x100>;
193 clocks = <&dfx_coredivclk 0>;
198 reg = <0xF0900 0x100
199 0xF0B00 0x100>;
221 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
222 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
226 reg = <0xf8204 0x4>;
232 reg = <0xf8268 0xc>;
243 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
245 pp0: packet-processor@0 {
247 reg = <0 0x4000000>;
258 #clock-cells = <0>;
266 reg = <0x11000 0x100>;
271 reg = <0x11100 0x100>;
275 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
295 reg = <0x20800 0x20>;
331 pinctrl-0 = <&spi0_pins>;