Lines Matching +full:0 +full:x80000

20 		#size-cells = <0>;
23 		cpu@0 {
26 			reg = <0>;
45 			bus-range = <0x00 0xff>;
48 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
49 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
50 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
51 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
52 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
53 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
54 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
55 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
56 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
57 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
58 				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
64 			 * pcie@4,0 is not available.
66 			pcie1: pcie@1,0 {
68 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
69 				reg = <0x0800 0 0 0 0>;
73 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
74 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
75 				bus-range = <0x00 0xff>;
76 				interrupt-map-mask = <0 0 0 0>;
77 				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
78 				marvell,pcie-port = <0>;
79 				marvell,pcie-lane = <0>;
85 			pcie2: pcie@2,0 {
87 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
88 				reg = <0x1000 0 0 0 0>;
92 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
93 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
94 				bus-range = <0x00 0xff>;
95 				interrupt-map-mask = <0 0 0 0>;
96 				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
98 				marvell,pcie-lane = <0>;
104 			pcie3: pcie@3,0 {
106 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
107 				reg = <0x1800 0 0 0 0>;
111 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
112 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
113 				bus-range = <0x00 0xff>;
114 				interrupt-map-mask = <0 0 0 0>;
115 				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
117 				marvell,pcie-lane = <0>;
123 			 * x1 port only available when pcie@1,0 is
126 			pcie4: pcie@4,0 {
128 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
129 				reg = <0x2000 0 0 0 0>;
133 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
134 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
135 				bus-range = <0x00 0xff>;
136 				interrupt-map-mask = <0 0 0 0>;
137 				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
139 				marvell,pcie-lane = <0>;