Lines Matching +full:0 +full:x40000

20 		#size-cells = <0>;
23 		cpu@0 {
26 			reg = <0>;
46 			bus-range = <0x00 0xff>;
49 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
55 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
56 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
57 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
58 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
61 			pcie@1,0 {
63 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
64 				reg = <0x0800 0 0 0 0>;
68 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
69 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
70 				bus-range = <0x00 0xff>;
71 				interrupt-map-mask = <0 0 0 0>;
72 				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
73 				marvell,pcie-port = <0>;
74 				marvell,pcie-lane = <0>;
80 			pcie@2,0 {
82 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 				reg = <0x1000 0 0 0 0>;
87 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
88 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
89 				bus-range = <0x00 0xff>;
90 				interrupt-map-mask = <0 0 0 0>;
91 				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
93 				marvell,pcie-lane = <0>;
99 			pcie@3,0 {
101 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
102 				reg = <0x1800 0 0 0 0>;
106 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
107 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
108 				bus-range = <0x00 0xff>;
109 				interrupt-map-mask = <0 0 0 0>;
110 				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
112 				marvell,pcie-lane = <0>;