Lines Matching +full:mv64xxx +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <1000000000>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "marvell,armada-375-smp";
54 compatible = "arm,cortex-a9";
59 compatible = "arm,cortex-a9";
65 compatible = "arm,cortex-a9-pmu";
66 interrupts-extended = <&mpic 3>;
70 compatible = "marvell,armada375-mbus", "simple-bus";
71 #address-cells = <2>;
72 #size-cells = <1>;
74 interrupt-parent = <&gic>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
83 devbus_bootcs: devbus-bootcs {
84 compatible = "marvell,mvebu-devbus";
87 #address-cells = <1>;
88 #size-cells = <1>;
93 devbus_cs0: devbus-cs0 {
94 compatible = "marvell,mvebu-devbus";
97 #address-cells = <1>;
98 #size-cells = <1>;
103 devbus_cs1: devbus-cs1 {
104 compatible = "marvell,mvebu-devbus";
107 #address-cells = <1>;
108 #size-cells = <1>;
113 devbus_cs2: devbus-cs2 {
114 compatible = "marvell,mvebu-devbus";
117 #address-cells = <1>;
118 #size-cells = <1>;
123 devbus_cs3: devbus-cs3 {
124 compatible = "marvell,mvebu-devbus";
127 #address-cells = <1>;
128 #size-cells = <1>;
133 internal-regs {
134 compatible = "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
139 L2: cache-controller@8000 {
140 compatible = "arm,pl310-cache";
142 cache-unified;
143 cache-level = <2>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
147 prefetch-data = <1>;
151 compatible = "arm,cortex-a9-scu";
156 compatible = "arm,cortex-a9-twd-timer";
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "marvell,orion-mdio";
181 compatible = "marvell,armada-375-pp2";
187 clock-names = "pp_clk", "gop_clk";
192 port-id = <0>;
198 port-id = <1>;
204 compatible = "marvell,orion-rtc";
210 compatible = "marvell,armada-375-spi",
211 "marvell,orion-spi";
213 #address-cells = <1>;
214 #size-cells = <0>;
215 cell-index = <0>;
222 compatible = "marvell,armada-375-spi",
223 "marvell,orion-spi";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 cell-index = <1>;
233 i2c0: i2c@11000 {
234 compatible = "marvell,mv64xxx-i2c";
236 #address-cells = <1>;
237 #size-cells = <0>;
243 i2c1: i2c@11100 {
244 compatible = "marvell,mv64xxx-i2c";
246 #address-cells = <1>;
247 #size-cells = <0>;
254 compatible = "snps,dw-apb-uart";
256 reg-shift = <2>;
258 reg-io-width = <1>;
264 compatible = "snps,dw-apb-uart";
266 reg-shift = <2>;
268 reg-io-width = <1>;
274 compatible = "marvell,mv88f6720-pinctrl";
277 i2c0_pins: i2c0-pins {
282 i2c1_pins: i2c1-pins {
287 nand_pins: nand-pins {
296 sdio_pins: sdio-pins {
302 spi0_pins: spi0-pins {
310 compatible = "marvell,orion-gpio";
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
324 compatible = "marvell,orion-gpio";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
338 compatible = "marvell,orion-gpio";
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
348 systemc: system-controller@18200 {
349 compatible = "marvell,armada-375-system-controller";
353 gateclk: clock-gating-control@18220 {
354 compatible = "marvell,armada-375-gating-clock";
357 #clock-cells = <1>;
360 usbcluster: usb-cluster@18400 {
361 compatible = "marvell,armada-375-usb-cluster";
363 #phy-cells = <1>;
366 mbusc: mbus-controller@20000 {
367 compatible = "marvell,mbus-controller";
371 mpic: interrupt-controller@20a00 {
374 #interrupt-cells = <1>;
375 #size-cells = <1>;
376 interrupt-controller;
377 msi-controller;
382 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
384 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
391 clock-names = "nbclk", "fixed";
395 compatible = "marvell,armada-375-wdt";
398 clock-names = "nbclk", "fixed";
402 compatible = "marvell,armada-370-cpu-reset";
406 coherencyfab: coherency-fabric@21010 {
407 compatible = "marvell,armada-375-coherency-fabric";
412 compatible = "marvell,orion-ehci";
417 phy-names = "usb";
422 compatible = "marvell,orion-ehci";
430 compatible = "marvell,armada-375-xhci";
435 phy-names = "usb";
440 compatible = "marvell,orion-xor";
460 compatible = "marvell,orion-xor";
480 compatible = "marvell,armada-375-crypto";
482 reg-names = "regs";
487 clock-names = "cesa0", "cesa1",
489 marvell,crypto-srams = <&crypto_sram0>,
491 marvell,crypto-sram-size = <0x800>;
495 compatible = "marvell,armada-370-sata";
499 clock-names = "0", "1";
503 nand_controller: nand-controller@d0000 {
504 compatible = "marvell,armada370-nand-controller";
506 #address-cells = <1>;
507 #size-cells = <0>;
514 compatible = "marvell,orion-sdio";
518 bus-width = <4>;
519 cap-sdio-irq;
520 cap-sd-highspeed;
521 cap-mmc-highspeed;
526 compatible = "marvell,armada375-thermal";
531 coreclk: mvebu-sar@e8204 {
532 compatible = "marvell,armada-375-core-clock";
534 #clock-cells = <1>;
537 coredivclk: corediv-clock@e8250 {
538 compatible = "marvell,armada-375-corediv-clock";
540 #clock-cells = <1>;
542 clock-output-names = "nand";
547 compatible = "marvell,armada-370-pcie";
551 #address-cells = <3>;
552 #size-cells = <2>;
554 msi-parent = <&mpic>;
555 bus-range = <0x00 0xff>;
567 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
569 #address-cells = <3>;
570 #size-cells = <2>;
571 #interrupt-cells = <1>;
574 bus-range = <0x00 0xff>;
575 interrupt-map-mask = <0 0 0 0>;
576 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
577 marvell,pcie-port = <0>;
578 marvell,pcie-lane = <0>;
585 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
587 #address-cells = <3>;
588 #size-cells = <2>;
589 #interrupt-cells = <1>;
592 bus-range = <0x00 0xff>;
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
595 marvell,pcie-port = <0>;
596 marvell,pcie-lane = <1>;
603 crypto_sram0: sa-sram0 {
604 compatible = "mmio-sram";
607 #address-cells = <1>;
608 #size-cells = <1>;
612 crypto_sram1: sa-sram1 {
613 compatible = "mmio-sram";
616 #address-cells = <1>;
617 #size-cells = <1>;