Lines Matching +full:0 +full:x800000
11 * internal registers to 0xf1000000 (instead of the default
12 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
36 reg = <0x00000000 0x20000000>; /* 512 MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
59 pinctrl-0 = <&ge1_rgmii_pins>;
70 pinctrl-0 = <&sdio_pins1>;
88 #size-cells = <0>;
99 gpio-fan,speed-map = <0 0 3000 1>;
100 pinctrl-0 = <&fan_pins>;
107 pinctrl-0 = <&led_pins>;
111 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
123 pcie@1,0 {
124 /* Port 0, Lane 0 */
129 pcie@2,0 {
130 /* Port 1, Lane 0 */
136 pinctrl-0 = <&mdio_pins>;
138 phy0: ethernet-phy@0 {
139 reg = <0>;
145 #size-cells = <0>;
146 reg = <0x10>;
152 #size-cells = <0>;
154 port@0 {
155 reg = <0>;
187 #size-cells = <0>;
189 switchphy0: switchphy@0 {
190 reg = <0>;
192 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
232 nand@0 {
233 reg = <0>;
234 label = "pxa3xx_nand-0";
235 nand-rb = <0>;
244 partition@0 {
246 reg = <0 0x800000>;
250 reg = <0x800000 0x800000>;
254 reg = <0x1000000 0x3f000000>;