Lines Matching +full:0 +full:x3a000000
45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
81 #clock-cells = <0>;
89 #clock-cells = <0>;
97 #clock-cells = <0>;
105 #clock-cells = <0>;
113 pclk: pclk@0 {
114 #clock-cells = <0>;
116 clock-frequency = <0>;
121 reg = <0x30000000 0x4000000>;
130 reg = <0x38000000 0x800000>;
145 reg = <0x3c000000 0x4000000>;
153 reg = <0x3a000000 0x10000>;
155 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
166 reg = <0x3b000000 0x20000>;
168 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
175 #size-cells = <0>;
179 #size-cells = <0>;
181 port@0 {
182 reg = <0>;
218 reg = <0x10000000 0x1000>;
222 offset = <0x08>;
223 mask = <0x01>;
224 label = "versatile:0";
230 offset = <0x08>;
231 mask = <0x02>;
238 offset = <0x08>;
239 mask = <0x04>;
246 offset = <0x08>;
247 mask = <0x08>;
253 offset = <0x08>;
254 mask = <0x10>;
260 offset = <0x08>;
261 mask = <0x20>;
267 offset = <0x08>;
268 mask = <0x40>;
274 offset = <0x08>;
275 mask = <0x80>;
279 oscclk0: osc0@0c {
281 #clock-cells = <0>;
282 lock-offset = <0x20>;
283 vco-offset = <0x0C>;
288 #clock-cells = <0>;
289 lock-offset = <0x20>;
290 vco-offset = <0x10>;
295 #clock-cells = <0>;
296 lock-offset = <0x20>;
297 vco-offset = <0x14>;
302 #clock-cells = <0>;
303 lock-offset = <0x20>;
304 vco-offset = <0x18>;
309 #clock-cells = <0>;
310 lock-offset = <0x20>;
311 vco-offset = <0x1c>;
322 reg = <0x10121000 0x1000>,
323 <0x10120000 0x100>;
328 reg = <0x10110000 0x1000>;
330 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
347 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
352 reg = <0x10104000 0x1000>;
354 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
361 reg = <0x10105000 0x1000>;
363 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
371 reg = <0x10108000 0x1000>;
373 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
380 reg = <0x1010a000 0x1000>;
383 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
393 reg = <0x1010b000 0x1000>;
395 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
402 reg = <0x1010c000 0x1000>;
404 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
411 reg = <0x1010d000 0x1000>;
413 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
420 reg = <0x1010e000 0x1000>;
422 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
429 reg = <0x1010f000 0x1000>;
431 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
439 reg = <0x10200000 0x4000>;
445 reg = <0x10112000 0x1000>;
448 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
457 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
472 #size-cells = <0>;
474 reg = <0x10002000 0x1000>;
478 reg = <0x68>;
484 reg = <0x10004000 0x1000>;
486 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
493 reg = <0x10005000 0x1000>;
495 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
496 <0 2 IRQ_TYPE_LEVEL_HIGH>;
505 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
511 reg = <0x10006000 0x1000>;
513 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
520 reg = <0x10007000 0x1000>;
522 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
529 reg = <0x10008000 0x1000>;
531 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
538 reg = <0x10009000 0x1000>;
540 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
551 reg = <0x10041000 0x1000>,
552 <0x10040000 0x100>;
554 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
559 reg = <0x10014000 0x1000>;
562 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
572 reg = <0x10015000 0x1000>;
575 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0x10017000 0x1000>;
587 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;