Lines Matching +full:0 +full:x26000
1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
19 <0x00000800 0x00000800 0x000800>, /* ap 1 */
20 <0x00001000 0x00001000 0x000400>, /* ap 2 */
21 <0x00001400 0x00001400 0x000400>; /* ap 3 */
24 segment@100000 { /* 0x44d00000 */
28 ranges = <0x00000000 0x00100000 0x004000>, /* ap 4 */
29 <0x00004000 0x00104000 0x001000>, /* ap 5 */
30 <0x00080000 0x00180000 0x002000>, /* ap 6 */
31 <0x00082000 0x00182000 0x001000>, /* ap 7 */
32 <0x000f0000 0x001f0000 0x010000>; /* ap 8 */
34 target-module@0 { /* 0x44d00000, ap 4 28.0 */
39 ranges = <0x0 0x0 0x4000>;
42 target-module@80000 { /* 0x44d80000, ap 6 10.0 */
47 ranges = <0x0 0x80000 0x2000>;
50 target-module@f0000 { /* 0x44df0000, ap 8 58.0 */
52 reg = <0xf0000 0x4>;
56 ranges = <0x0 0xf0000 0x10000>;
58 prcm: prcm@0 {
60 reg = <0x0 0x11000>;
64 ranges = <0 0 0x11000>;
68 #size-cells = <0>;
77 segment@200000 { /* 0x44e00000 */
81 ranges = <0x00000000 0x00200000 0x001000>, /* ap 9 */
82 <0x00003000 0x00203000 0x001000>, /* ap 10 */
83 <0x00004000 0x00204000 0x001000>, /* ap 11 */
84 <0x00005000 0x00205000 0x001000>, /* ap 12 */
85 <0x00006000 0x00206000 0x001000>, /* ap 13 */
86 <0x00007000 0x00207000 0x001000>, /* ap 14 */
87 <0x00008000 0x00208000 0x001000>, /* ap 15 */
88 <0x00009000 0x00209000 0x001000>, /* ap 16 */
89 <0x0000a000 0x0020a000 0x001000>, /* ap 17 */
90 <0x0000b000 0x0020b000 0x001000>, /* ap 18 */
91 <0x0000c000 0x0020c000 0x001000>, /* ap 19 */
92 <0x0000d000 0x0020d000 0x001000>, /* ap 20 */
93 <0x0000f000 0x0020f000 0x001000>, /* ap 21 */
94 <0x00010000 0x00210000 0x010000>, /* ap 22 */
95 <0x00030000 0x00230000 0x001000>, /* ap 23 */
96 <0x00031000 0x00231000 0x001000>, /* ap 24 */
97 <0x00032000 0x00232000 0x001000>, /* ap 25 */
98 <0x00033000 0x00233000 0x001000>, /* ap 26 */
99 <0x00034000 0x00234000 0x001000>, /* ap 27 */
100 <0x00035000 0x00235000 0x001000>, /* ap 28 */
101 <0x00036000 0x00236000 0x001000>, /* ap 29 */
102 <0x00037000 0x00237000 0x001000>, /* ap 30 */
103 <0x00038000 0x00238000 0x001000>, /* ap 31 */
104 <0x00039000 0x00239000 0x001000>, /* ap 32 */
105 <0x0003a000 0x0023a000 0x001000>, /* ap 33 */
106 <0x0003e000 0x0023e000 0x001000>, /* ap 34 */
107 <0x0003f000 0x0023f000 0x001000>, /* ap 35 */
108 <0x00040000 0x00240000 0x040000>, /* ap 36 */
109 <0x00080000 0x00280000 0x001000>, /* ap 37 */
110 <0x00088000 0x00288000 0x008000>, /* ap 38 */
111 <0x00092000 0x00292000 0x001000>, /* ap 39 */
112 <0x00086000 0x00286000 0x001000>, /* ap 40 */
113 <0x00087000 0x00287000 0x001000>, /* ap 41 */
114 <0x00090000 0x00290000 0x001000>, /* ap 42 */
115 <0x00091000 0x00291000 0x001000>; /* ap 43 */
117 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */
122 ranges = <0x0 0x3000 0x1000>;
125 target-module@5000 { /* 0x44e05000, ap 12 30.0 */
130 ranges = <0x0 0x5000 0x1000>;
133 target-module@7000 { /* 0x44e07000, ap 14 20.0 */
135 reg = <0x7000 0x4>,
136 <0x7010 0x4>,
137 <0x7114 0x4>;
148 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_GPIO1_CLKCTRL 0>,
153 ranges = <0x0 0x7000 0x1000>;
155 gpio0: gpio@0 {
157 reg = <0x0 0x1000>;
167 target-module@9000 { /* 0x44e09000, ap 16 04.0 */
169 reg = <0x9050 0x4>,
170 <0x9054 0x4>,
171 <0x9058 0x4>;
181 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_UART1_CLKCTRL 0>;
185 ranges = <0x0 0x9000 0x1000>;
187 uart0: serial@0 {
189 reg = <0x0 0x2000>;
194 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */
196 reg = <0xb000 0x8>,
197 <0xb010 0x8>,
198 <0xb090 0x8>;
210 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_I2C1_CLKCTRL 0>;
214 ranges = <0x0 0xb000 0x1000>;
216 i2c0: i2c@0 {
218 reg = <0x0 0x1000>;
221 #size-cells = <0>;
226 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */
228 reg = <0xd000 0x4>,
229 <0xd010 0x4>;
236 clocks = <&l3s_tsc_clkctrl AM4_L3S_TSC_ADC_TSC_CLKCTRL 0>;
240 ranges = <0x0 0xd000 0x1000>;
242 tscadc: tscadc@0 {
244 reg = <0x0 0x1000>;
249 dmas = <&edma 53 0>, <&edma 57 0>;
264 target-module@10000 { /* 0x44e10000, ap 22 0c.0 */
266 reg = <0x10000 0x4>;
270 ranges = <0x0 0x10000 0x10000>;
272 scm: scm@0 {
274 reg = <0x0 0x4000>;
277 ranges = <0 0 0x4000>;
282 reg = <0x800 0x31c>;
284 #size-cells = <0>;
289 pinctrl-single,function-mask = <0xffffffff>;
292 scm_conf: scm_conf@0 {
294 reg = <0x0 0x800>;
300 reg = <0x650 0x4>;
306 #size-cells = <0>;
312 reg = <0x1324 0x44>;
320 reg = <0xf90 0x40>;
331 timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
333 reg = <0x31000 0x4>,
334 <0x31010 0x4>,
335 <0x31014 0x4>;
345 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>;
349 ranges = <0x0 0x31000 0x1000>;
351 timer1: timer@0 {
353 reg = <0x0 0x400>;
361 target-module@33000 { /* 0x44e33000, ap 26 18.0 */
366 ranges = <0x0 0x33000 0x1000>;
369 target-module@35000 { /* 0x44e35000, ap 28 50.0 */
371 reg = <0x35000 0x4>,
372 <0x35010 0x4>,
373 <0x35014 0x4>;
383 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_WD_TIMER2_CLKCTRL 0>;
387 ranges = <0x0 0x35000 0x1000>;
389 wdt: wdt@0 {
391 reg = <0x0 0x1000>;
396 target-module@37000 { /* 0x44e37000, ap 30 08.0 */
401 ranges = <0x0 0x37000 0x1000>;
404 target-module@39000 { /* 0x44e39000, ap 32 02.0 */
409 ranges = <0x0 0x39000 0x1000>;
412 rtc_target: target-module@3e000 { /* 0x44e3e000, ap 34 60.0 */
414 reg = <0x3e074 0x4>,
415 <0x3e078 0x4>;
422 clocks = <&l4_rtc_clkctrl AM4_L4_RTC_RTC_CLKCTRL 0>;
426 ranges = <0x0 0x3e000 0x1000>;
428 rtc: rtc@0 {
431 reg = <0x0 0x1000>;
441 target-module@40000 { /* 0x44e40000, ap 36 68.0 */
446 ranges = <0x0 0x40000 0x40000>;
449 target-module@86000 { /* 0x44e86000, ap 40 70.0 */
451 reg = <0x86000 0x4>,
452 <0x86004 0x4>;
457 clocks = <&l4_wkup_aon_clkctrl AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL 0>;
461 ranges = <0x0 0x86000 0x1000>;
463 counter32k: counter@0 {
465 reg = <0x0 0x40>;
469 target-module@88000 { /* 0x44e88000, ap 38 12.0 */
474 ranges = <0x00000000 0x00088000 0x00008000>,
475 <0x00008000 0x00090000 0x00001000>,
476 <0x00009000 0x00091000 0x00001000>;
481 &l4_fast { /* 0x4a000000 */
483 reg = <0x4a000000 0x800>,
484 <0x4a000800 0x800>,
485 <0x4a001000 0x400>;
489 ranges = <0x00000000 0x4a000000 0x1000000>; /* segment 0 */
491 segment@0 { /* 0x4a000000 */
495 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
496 <0x00000800 0x00000800 0x000800>, /* ap 1 */
497 <0x00001000 0x00001000 0x000400>, /* ap 2 */
498 <0x00100000 0x00100000 0x008000>, /* ap 3 */
499 <0x00108000 0x00108000 0x001000>, /* ap 4 */
500 <0x00400000 0x00400000 0x002000>, /* ap 5 */
501 <0x00402000 0x00402000 0x001000>, /* ap 6 */
502 <0x00200000 0x00200000 0x080000>, /* ap 7 */
503 <0x00280000 0x00280000 0x001000>; /* ap 8 */
505 target-module@100000 { /* 0x4a100000, ap 3 04.0 */
507 reg = <0x101200 0x4>,
508 <0x101208 0x4>,
509 <0x101204 0x4>;
511 ti,sysc-mask = <0>;
517 clocks = <&cpsw_125mhz_clkctrl AM4_CPSW_125MHZ_CPGMAC0_CLKCTRL 0>;
521 ranges = <0x0 0x100000 0x8000>;
523 mac_sw: switch@0 {
525 reg = <0x0 0x4000>;
526 ranges = <0 0 0x4000>;
544 #size-cells = <0>;
550 phys = <&phy_gmii_sel 1 0>;
557 phys = <&phy_gmii_sel 2 0>;
566 #size-cells = <0>;
568 reg = <0x1000 0x100>;
578 target-module@200000 { /* 0x4a200000, ap 7 02.0 */
583 ranges = <0x0 0x200000 0x80000>;
586 target-module@400000 { /* 0x4a400000, ap 5 08.0 */
591 ranges = <0x0 0x400000 0x2000>;
596 &l4_per { /* 0x48000000 */
598 reg = <0x48000000 0x800>,
599 <0x48000800 0x800>,
600 <0x48001000 0x400>,
601 <0x48001400 0x400>,
602 <0x48001800 0x400>,
603 <0x48001c00 0x400>;
607 ranges = <0x00000000 0x48000000 0x100000>, /* segment 0 */
608 <0x00100000 0x48100000 0x100000>, /* segment 1 */
609 <0x00200000 0x48200000 0x100000>, /* segment 2 */
610 <0x00300000 0x48300000 0x100000>, /* segment 3 */
611 <0x46000000 0x46000000 0x400000>, /* l3 data port */
612 <0x46400000 0x46400000 0x400000>; /* l3 data port */
614 segment@0 { /* 0x48000000 */
618 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
619 <0x00000800 0x00000800 0x000800>, /* ap 1 */
620 <0x00001000 0x00001000 0x000400>, /* ap 2 */
621 <0x00001400 0x00001400 0x000400>, /* ap 3 */
622 <0x00001800 0x00001800 0x000400>, /* ap 4 */
623 <0x00001c00 0x00001c00 0x000400>, /* ap 5 */
624 <0x00008000 0x00008000 0x001000>, /* ap 6 */
625 <0x00009000 0x00009000 0x001000>, /* ap 7 */
626 <0x00022000 0x00022000 0x001000>, /* ap 8 */
627 <0x00023000 0x00023000 0x001000>, /* ap 9 */
628 <0x00024000 0x00024000 0x001000>, /* ap 10 */
629 <0x00025000 0x00025000 0x001000>, /* ap 11 */
630 <0x0002a000 0x0002a000 0x001000>, /* ap 12 */
631 <0x0002b000 0x0002b000 0x001000>, /* ap 13 */
632 <0x00038000 0x00038000 0x002000>, /* ap 14 */
633 <0x0003a000 0x0003a000 0x001000>, /* ap 15 */
634 <0x0003c000 0x0003c000 0x002000>, /* ap 16 */
635 <0x0003e000 0x0003e000 0x001000>, /* ap 17 */
636 <0x00040000 0x00040000 0x001000>, /* ap 18 */
637 <0x00041000 0x00041000 0x001000>, /* ap 19 */
638 <0x00042000 0x00042000 0x001000>, /* ap 20 */
639 <0x00043000 0x00043000 0x001000>, /* ap 21 */
640 <0x00044000 0x00044000 0x001000>, /* ap 22 */
641 <0x00045000 0x00045000 0x001000>, /* ap 23 */
642 <0x00046000 0x00046000 0x001000>, /* ap 24 */
643 <0x00047000 0x00047000 0x001000>, /* ap 25 */
644 <0x00048000 0x00048000 0x001000>, /* ap 26 */
645 <0x00049000 0x00049000 0x001000>, /* ap 27 */
646 <0x0004c000 0x0004c000 0x001000>, /* ap 28 */
647 <0x0004d000 0x0004d000 0x001000>, /* ap 29 */
648 <0x00060000 0x00060000 0x001000>, /* ap 30 */
649 <0x00061000 0x00061000 0x001000>, /* ap 31 */
650 <0x00080000 0x00080000 0x010000>, /* ap 32 */
651 <0x00090000 0x00090000 0x001000>, /* ap 33 */
652 <0x00030000 0x00030000 0x001000>, /* ap 65 */
653 <0x00031000 0x00031000 0x001000>, /* ap 66 */
654 <0x0004a000 0x0004a000 0x001000>, /* ap 71 */
655 <0x0004b000 0x0004b000 0x001000>, /* ap 72 */
656 <0x000c8000 0x000c8000 0x001000>, /* ap 73 */
657 <0x000c9000 0x000c9000 0x001000>, /* ap 74 */
658 <0x000ca000 0x000ca000 0x001000>, /* ap 77 */
659 <0x000cb000 0x000cb000 0x001000>, /* ap 78 */
660 <0x00034000 0x00034000 0x001000>, /* ap 80 */
661 <0x00035000 0x00035000 0x001000>, /* ap 81 */
662 <0x00036000 0x00036000 0x001000>, /* ap 84 */
663 <0x00037000 0x00037000 0x001000>, /* ap 85 */
664 <0x46000000 0x46000000 0x400000>, /* l3 data port */
665 <0x46400000 0x46400000 0x400000>; /* l3 data port */
667 target-module@8000 { /* 0x48008000, ap 6 10.0 */
672 ranges = <0x0 0x8000 0x1000>;
675 target-module@22000 { /* 0x48022000, ap 8 0a.0 */
677 reg = <0x22050 0x4>,
678 <0x22054 0x4>,
679 <0x22058 0x4>;
689 clocks = <&l4ls_clkctrl AM4_L4LS_UART2_CLKCTRL 0>;
693 ranges = <0x0 0x22000 0x1000>;
695 uart1: serial@0 {
697 reg = <0x0 0x2000>;
703 target-module@24000 { /* 0x48024000, ap 10 1c.0 */
705 reg = <0x24050 0x4>,
706 <0x24054 0x4>,
707 <0x24058 0x4>;
717 clocks = <&l4ls_clkctrl AM4_L4LS_UART3_CLKCTRL 0>;
721 ranges = <0x0 0x24000 0x1000>;
723 uart2: serial@0 {
725 reg = <0x0 0x2000>;
731 target-module@2a000 { /* 0x4802a000, ap 12 22.0 */
733 reg = <0x2a000 0x8>,
734 <0x2a010 0x8>,
735 <0x2a090 0x8>;
747 clocks = <&l4ls_clkctrl AM4_L4LS_I2C2_CLKCTRL 0>;
751 ranges = <0x0 0x2a000 0x1000>;
753 i2c1: i2c@0 {
755 reg = <0x0 0x1000>;
758 #size-cells = <0>;
763 target-module@30000 { /* 0x48030000, ap 65 08.0 */
765 reg = <0x30000 0x4>,
766 <0x30110 0x4>,
767 <0x30114 0x4>;
777 clocks = <&l4ls_clkctrl AM4_L4LS_SPI0_CLKCTRL 0>;
781 ranges = <0x0 0x30000 0x1000>;
783 spi0: spi@0 {
785 reg = <0x0 0x400>;
788 #size-cells = <0>;
793 target-module@34000 { /* 0x48034000, ap 80 56.0 */
798 ranges = <0x0 0x34000 0x1000>;
801 target-module@36000 { /* 0x48036000, ap 84 3e.0 */
806 ranges = <0x0 0x36000 0x1000>;
809 target-module@38000 { /* 0x48038000, ap 14 04.0 */
811 reg = <0x38000 0x4>,
812 <0x38004 0x4>;
818 clocks = <&l3s_clkctrl AM4_L3S_MCASP0_CLKCTRL 0>;
822 ranges = <0x0 0x38000 0x2000>,
823 <0x46000000 0x46000000 0x400000>;
825 mcasp0: mcasp@0 {
827 reg = <0x0 0x2000>,
828 <0x46000000 0x400000>;
840 target-module@3c000 { /* 0x4803c000, ap 16 2a.0 */
842 reg = <0x3c000 0x4>,
843 <0x3c004 0x4>;
849 clocks = <&l3s_clkctrl AM4_L3S_MCASP1_CLKCTRL 0>;
853 ranges = <0x0 0x3c000 0x2000>,
854 <0x46400000 0x46400000 0x400000>;
856 mcasp1: mcasp@0 {
858 reg = <0x0 0x2000>,
859 <0x46400000 0x400000>;
871 timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
873 reg = <0x40000 0x4>,
874 <0x40010 0x4>,
875 <0x40014 0x4>;
883 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>;
887 ranges = <0x0 0x40000 0x1000>;
889 timer2: timer@0 {
891 reg = <0x0 0x400>;
898 target-module@42000 { /* 0x48042000, ap 20 24.0 */
900 reg = <0x42000 0x4>,
901 <0x42010 0x4>,
902 <0x42014 0x4>;
910 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER3_CLKCTRL 0>;
914 ranges = <0x0 0x42000 0x1000>;
916 timer3: timer@0 {
918 reg = <0x0 0x400>;
924 target-module@44000 { /* 0x48044000, ap 22 26.0 */
926 reg = <0x44000 0x4>,
927 <0x44010 0x4>,
928 <0x44014 0x4>;
936 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER4_CLKCTRL 0>;
940 ranges = <0x0 0x44000 0x1000>;
942 timer4: timer@0 {
944 reg = <0x0 0x400>;
951 target-module@46000 { /* 0x48046000, ap 24 28.0 */
953 reg = <0x46000 0x4>,
954 <0x46010 0x4>,
955 <0x46014 0x4>;
963 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER5_CLKCTRL 0>;
967 ranges = <0x0 0x46000 0x1000>;
969 timer5: timer@0 {
971 reg = <0x0 0x400>;
978 target-module@48000 { /* 0x48048000, ap 26 1a.0 */
980 reg = <0x48000 0x4>,
981 <0x48010 0x4>,
982 <0x48014 0x4>;
990 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER6_CLKCTRL 0>;
994 ranges = <0x0 0x48000 0x1000>;
996 timer6: timer@0 {
998 reg = <0x0 0x400>;
1005 target-module@4a000 { /* 0x4804a000, ap 71 48.0 */
1007 reg = <0x4a000 0x4>,
1008 <0x4a010 0x4>,
1009 <0x4a014 0x4>;
1017 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER7_CLKCTRL 0>;
1021 ranges = <0x0 0x4a000 0x1000>;
1023 timer7: timer@0 {
1025 reg = <0x0 0x400>;
1032 target-module@4c000 { /* 0x4804c000, ap 28 36.0 */
1034 reg = <0x4c000 0x4>,
1035 <0x4c010 0x4>,
1036 <0x4c114 0x4>;
1047 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO2_CLKCTRL 0>,
1052 ranges = <0x0 0x4c000 0x1000>;
1054 gpio1: gpio@0 {
1056 reg = <0x0 0x1000>;
1066 target-module@60000 { /* 0x48060000, ap 30 14.0 */
1068 reg = <0x602fc 0x4>,
1069 <0x60110 0x4>,
1070 <0x60114 0x4>;
1081 clocks = <&l4ls_clkctrl AM4_L4LS_MMC1_CLKCTRL 0>;
1085 ranges = <0x0 0x60000 0x1000>;
1087 mmc1: mmc@0 {
1089 reg = <0x0 0x1000>;
1091 dmas = <&edma 24 0>,
1092 <&edma 25 0>;
1099 target-module@80000 { /* 0x48080000, ap 32 18.0 */
1101 reg = <0x80000 0x4>,
1102 <0x80010 0x4>,
1103 <0x80014 0x4>;
1113 clocks = <&l4ls_clkctrl AM4_L4LS_ELM_CLKCTRL 0>;
1117 ranges = <0x0 0x80000 0x10000>;
1119 elm: elm@0 {
1121 reg = <0x0 0x2000>;
1129 target-module@c8000 { /* 0x480c8000, ap 73 06.0 */
1131 reg = <0xc8000 0x4>,
1132 <0xc8010 0x4>;
1139 clocks = <&l4ls_clkctrl AM4_L4LS_MAILBOX_CLKCTRL 0>;
1143 ranges = <0x0 0xc8000 0x1000>;
1145 mailbox: mailbox@0 {
1147 reg = <0x0 0x200>;
1154 ti,mbox-tx = <0 0 0>;
1155 ti,mbox-rx = <0 0 3>;
1160 target-module@ca000 { /* 0x480ca000, ap 77 38.0 */
1162 reg = <0xca000 0x4>,
1163 <0xca010 0x4>,
1164 <0xca014 0x4>;
1175 clocks = <&l4ls_clkctrl AM4_L4LS_SPINLOCK_CLKCTRL 0>;
1179 ranges = <0x0 0xca000 0x1000>;
1181 hwspinlock: spinlock@0 {
1183 reg = <0x0 0x1000>;
1189 segment@100000 { /* 0x48100000 */
1193 ranges = <0x0008c000 0x0018c000 0x001000>, /* ap 34 */
1194 <0x0008d000 0x0018d000 0x001000>, /* ap 35 */
1195 <0x0008e000 0x0018e000 0x001000>, /* ap 36 */
1196 <0x0008f000 0x0018f000 0x001000>, /* ap 37 */
1197 <0x0009c000 0x0019c000 0x001000>, /* ap 38 */
1198 <0x0009d000 0x0019d000 0x001000>, /* ap 39 */
1199 <0x000a6000 0x001a6000 0x001000>, /* ap 40 */
1200 <0x000a7000 0x001a7000 0x001000>, /* ap 41 */
1201 <0x000a8000 0x001a8000 0x001000>, /* ap 42 */
1202 <0x000a9000 0x001a9000 0x001000>, /* ap 43 */
1203 <0x000aa000 0x001aa000 0x001000>, /* ap 44 */
1204 <0x000ab000 0x001ab000 0x001000>, /* ap 45 */
1205 <0x000ac000 0x001ac000 0x001000>, /* ap 46 */
1206 <0x000ad000 0x001ad000 0x001000>, /* ap 47 */
1207 <0x000ae000 0x001ae000 0x001000>, /* ap 48 */
1208 <0x000af000 0x001af000 0x001000>, /* ap 49 */
1209 <0x000cc000 0x001cc000 0x002000>, /* ap 50 */
1210 <0x000ce000 0x001ce000 0x002000>, /* ap 51 */
1211 <0x000d0000 0x001d0000 0x002000>, /* ap 52 */
1212 <0x000d2000 0x001d2000 0x002000>, /* ap 53 */
1213 <0x000d8000 0x001d8000 0x001000>, /* ap 54 */
1214 <0x000d9000 0x001d9000 0x001000>, /* ap 55 */
1215 <0x000a0000 0x001a0000 0x001000>, /* ap 67 */
1216 <0x000a1000 0x001a1000 0x001000>, /* ap 68 */
1217 <0x000a2000 0x001a2000 0x001000>, /* ap 69 */
1218 <0x000a3000 0x001a3000 0x001000>, /* ap 70 */
1219 <0x000a4000 0x001a4000 0x001000>, /* ap 92 */
1220 <0x000a5000 0x001a5000 0x001000>, /* ap 93 */
1221 <0x000c1000 0x001c1000 0x001000>, /* ap 94 */
1222 <0x000c2000 0x001c2000 0x001000>; /* ap 95 */
1224 target-module@8c000 { /* 0x4818c000, ap 34 0c.0 */
1229 ranges = <0x0 0x8c000 0x1000>;
1232 target-module@8e000 { /* 0x4818e000, ap 36 02.0 */
1237 ranges = <0x0 0x8e000 0x1000>;
1240 target-module@9c000 { /* 0x4819c000, ap 38 52.0 */
1242 reg = <0x9c000 0x8>,
1243 <0x9c010 0x8>,
1244 <0x9c090 0x8>;
1256 clocks = <&l4ls_clkctrl AM4_L4LS_I2C3_CLKCTRL 0>;
1260 ranges = <0x0 0x9c000 0x1000>;
1262 i2c2: i2c@0 {
1264 reg = <0x0 0x1000>;
1267 #size-cells = <0>;
1272 target-module@a0000 { /* 0x481a0000, ap 67 2c.0 */
1274 reg = <0xa0000 0x4>,
1275 <0xa0110 0x4>,
1276 <0xa0114 0x4>;
1286 clocks = <&l4ls_clkctrl AM4_L4LS_SPI1_CLKCTRL 0>;
1290 ranges = <0x0 0xa0000 0x1000>;
1292 spi1: spi@0 {
1294 reg = <0x0 0x400>;
1297 #size-cells = <0>;
1302 target-module@a2000 { /* 0x481a2000, ap 69 2e.0 */
1304 reg = <0xa2000 0x4>,
1305 <0xa2110 0x4>,
1306 <0xa2114 0x4>;
1316 clocks = <&l4ls_clkctrl AM4_L4LS_SPI2_CLKCTRL 0>;
1320 ranges = <0x0 0xa2000 0x1000>;
1322 spi2: spi@0 {
1324 reg = <0x0 0x400>;
1327 #size-cells = <0>;
1332 target-module@a4000 { /* 0x481a4000, ap 92 62.0 */
1334 reg = <0xa4000 0x4>,
1335 <0xa4110 0x4>,
1336 <0xa4114 0x4>;
1346 clocks = <&l4ls_clkctrl AM4_L4LS_SPI3_CLKCTRL 0>;
1350 ranges = <0x0 0xa4000 0x1000>;
1352 spi3: spi@0 {
1354 reg = <0x0 0x400>;
1357 #size-cells = <0>;
1362 target-module@a6000 { /* 0x481a6000, ap 40 16.0 */
1364 reg = <0xa6050 0x4>,
1365 <0xa6054 0x4>,
1366 <0xa6058 0x4>;
1376 clocks = <&l4ls_clkctrl AM4_L4LS_UART4_CLKCTRL 0>;
1380 ranges = <0x0 0xa6000 0x1000>;
1382 uart3: serial@0 {
1384 reg = <0x0 0x2000>;
1390 target-module@a8000 { /* 0x481a8000, ap 42 20.0 */
1392 reg = <0xa8050 0x4>,
1393 <0xa8054 0x4>,
1394 <0xa8058 0x4>;
1404 clocks = <&l4ls_clkctrl AM4_L4LS_UART5_CLKCTRL 0>;
1408 ranges = <0x0 0xa8000 0x1000>;
1410 uart4: serial@0 {
1412 reg = <0x0 0x2000>;
1418 target-module@aa000 { /* 0x481aa000, ap 44 12.0 */
1420 reg = <0xaa050 0x4>,
1421 <0xaa054 0x4>,
1422 <0xaa058 0x4>;
1432 clocks = <&l4ls_clkctrl AM4_L4LS_UART6_CLKCTRL 0>;
1436 ranges = <0x0 0xaa000 0x1000>;
1438 uart5: serial@0 {
1440 reg = <0x0 0x2000>;
1446 target-module@ac000 { /* 0x481ac000, ap 46 30.0 */
1448 reg = <0xac000 0x4>,
1449 <0xac010 0x4>,
1450 <0xac114 0x4>;
1461 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO3_CLKCTRL 0>,
1466 ranges = <0x0 0xac000 0x1000>;
1468 gpio2: gpio@0 {
1470 reg = <0x0 0x1000>;
1480 target-module@ae000 { /* 0x481ae000, ap 48 32.0 */
1482 reg = <0xae000 0x4>,
1483 <0xae010 0x4>,
1484 <0xae114 0x4>;
1495 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO4_CLKCTRL 0>,
1500 ranges = <0x0 0xae000 0x1000>;
1502 gpio3: gpio@0 {
1504 reg = <0x0 0x1000>;
1514 target-module@c1000 { /* 0x481c1000, ap 94 68.0 */
1516 reg = <0xc1000 0x4>,
1517 <0xc1010 0x4>,
1518 <0xc1014 0x4>;
1526 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER8_CLKCTRL 0>;
1530 ranges = <0x0 0xc1000 0x1000>;
1532 timer8: timer@0 {
1534 reg = <0x0 0x400>;
1540 target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
1542 reg = <0xcc020 0x4>;
1545 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>,
1550 ranges = <0x0 0xcc000 0x2000>;
1552 dcan0: can@0 {
1554 reg = <0x0 0x2000>;
1557 syscon-raminit = <&scm_conf 0x644 0>;
1563 target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
1565 reg = <0xd0020 0x4>;
1568 clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>,
1573 ranges = <0x0 0xd0000 0x2000>;
1575 dcan1: can@0 {
1577 reg = <0x0 0x2000>;
1580 syscon-raminit = <&scm_conf 0x644 1>;
1586 target-module@d8000 { /* 0x481d8000, ap 54 5e.0 */
1588 reg = <0xd82fc 0x4>,
1589 <0xd8110 0x4>,
1590 <0xd8114 0x4>;
1601 clocks = <&l4ls_clkctrl AM4_L4LS_MMC2_CLKCTRL 0>;
1605 ranges = <0x0 0xd8000 0x1000>;
1607 mmc2: mmc@0 {
1609 reg = <0x0 0x1000>;
1611 dmas = <&edma 2 0>,
1612 <&edma 3 0>;
1620 segment@200000 { /* 0x48200000 */
1626 segment@300000 { /* 0x48300000 */
1630 ranges = <0x00000000 0x00300000 0x001000>, /* ap 56 */
1631 <0x00001000 0x00301000 0x001000>, /* ap 57 */
1632 <0x00002000 0x00302000 0x001000>, /* ap 58 */
1633 <0x00003000 0x00303000 0x001000>, /* ap 59 */
1634 <0x00004000 0x00304000 0x001000>, /* ap 60 */
1635 <0x00005000 0x00305000 0x001000>, /* ap 61 */
1636 <0x00018000 0x00318000 0x004000>, /* ap 62 */
1637 <0x0001c000 0x0031c000 0x001000>, /* ap 63 */
1638 <0x00010000 0x00310000 0x002000>, /* ap 64 */
1639 <0x00028000 0x00328000 0x001000>, /* ap 75 */
1640 <0x00029000 0x00329000 0x001000>, /* ap 76 */
1641 <0x00012000 0x00312000 0x001000>, /* ap 79 */
1642 <0x00020000 0x00320000 0x001000>, /* ap 82 */
1643 <0x00021000 0x00321000 0x001000>, /* ap 83 */
1644 <0x00026000 0x00326000 0x001000>, /* ap 86 */
1645 <0x00027000 0x00327000 0x001000>, /* ap 87 */
1646 <0x0002a000 0x0032a000 0x000400>, /* ap 88 */
1647 <0x0002c000 0x0032c000 0x001000>, /* ap 89 */
1648 <0x00013000 0x00313000 0x001000>, /* ap 90 */
1649 <0x00014000 0x00314000 0x001000>, /* ap 91 */
1650 <0x00006000 0x00306000 0x001000>, /* ap 96 */
1651 <0x00007000 0x00307000 0x001000>, /* ap 97 */
1652 <0x00008000 0x00308000 0x001000>, /* ap 98 */
1653 <0x00009000 0x00309000 0x001000>, /* ap 99 */
1654 <0x0000a000 0x0030a000 0x001000>, /* ap 100 */
1655 <0x0000b000 0x0030b000 0x001000>, /* ap 101 */
1656 <0x0003d000 0x0033d000 0x001000>, /* ap 102 */
1657 <0x0003e000 0x0033e000 0x001000>, /* ap 103 */
1658 <0x0003f000 0x0033f000 0x001000>, /* ap 104 */
1659 <0x00040000 0x00340000 0x001000>, /* ap 105 */
1660 <0x00041000 0x00341000 0x001000>, /* ap 106 */
1661 <0x00042000 0x00342000 0x001000>, /* ap 107 */
1662 <0x00045000 0x00345000 0x001000>, /* ap 108 */
1663 <0x00046000 0x00346000 0x001000>, /* ap 109 */
1664 <0x00047000 0x00347000 0x001000>, /* ap 110 */
1665 <0x00048000 0x00348000 0x001000>, /* ap 111 */
1666 <0x000f2000 0x003f2000 0x002000>, /* ap 112 */
1667 <0x000f4000 0x003f4000 0x001000>, /* ap 113 */
1668 <0x0004c000 0x0034c000 0x002000>, /* ap 114 */
1669 <0x0004e000 0x0034e000 0x001000>, /* ap 115 */
1670 <0x00022000 0x00322000 0x001000>, /* ap 116 */
1671 <0x00023000 0x00323000 0x001000>, /* ap 117 */
1672 <0x000f0000 0x003f0000 0x001000>, /* ap 118 */
1673 <0x0002a400 0x0032a400 0x000400>, /* ap 119 */
1674 <0x0002a800 0x0032a800 0x000400>, /* ap 120 */
1675 <0x0002ac00 0x0032ac00 0x000400>, /* ap 121 */
1676 <0x0002b000 0x0032b000 0x001000>, /* ap 122 */
1677 <0x00080000 0x00380000 0x020000>, /* ap 123 */
1678 <0x000a0000 0x003a0000 0x001000>, /* ap 124 */
1679 <0x000a8000 0x003a8000 0x008000>, /* ap 125 */
1680 <0x000b0000 0x003b0000 0x001000>, /* ap 126 */
1681 <0x000c0000 0x003c0000 0x020000>, /* ap 127 */
1682 <0x000e0000 0x003e0000 0x001000>, /* ap 128 */
1683 <0x000e8000 0x003e8000 0x008000>; /* ap 129 */
1685 target-module@0 { /* 0x48300000, ap 56 40.0 */
1687 reg = <0x0 0x4>,
1688 <0x4 0x4>;
1699 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS0_CLKCTRL 0>;
1703 ranges = <0x0 0x0 0x1000>;
1705 epwmss0: epwmss@0 {
1707 reg = <0x0 0x10>;
1710 ranges = <0 0 0x1000>;
1718 reg = <0x100 0x80>;
1729 reg = <0x200 0x80>;
1737 target-module@2000 { /* 0x48302000, ap 58 4a.0 */
1739 reg = <0x2000 0x4>,
1740 <0x2004 0x4>;
1751 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS1_CLKCTRL 0>;
1755 ranges = <0x0 0x2000 0x1000>;
1757 epwmss1: epwmss@0 {
1759 reg = <0x0 0x10>;
1762 ranges = <0 0 0x1000>;
1770 reg = <0x100 0x80>;
1781 reg = <0x200 0x80>;
1789 target-module@4000 { /* 0x48304000, ap 60 44.0 */
1791 reg = <0x4000 0x4>,
1792 <0x4004 0x4>;
1803 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS2_CLKCTRL 0>;
1807 ranges = <0x0 0x4000 0x1000>;
1809 epwmss2: epwmss@0 {
1811 reg = <0x0 0x10>;
1814 ranges = <0 0 0x1000>;
1822 reg = <0x100 0x80>;
1833 reg = <0x200 0x80>;
1841 target-module@6000 { /* 0x48306000, ap 96 58.0 */
1843 reg = <0x6000 0x4>,
1844 <0x6004 0x4>;
1855 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS3_CLKCTRL 0>;
1859 ranges = <0x0 0x6000 0x1000>;
1861 epwmss3: epwmss@0 {
1863 reg = <0x0 0x10>;
1866 ranges = <0 0 0x1000>;
1874 reg = <0x200 0x80>;
1882 target-module@8000 { /* 0x48308000, ap 98 54.0 */
1884 reg = <0x8000 0x4>,
1885 <0x8004 0x4>;
1896 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS4_CLKCTRL 0>;
1900 ranges = <0x0 0x8000 0x1000>;
1902 epwmss4: epwmss@0 {
1904 reg = <0x0 0x10>;
1907 ranges = <0 0 0x1000>;
1915 reg = <0x200 0x80>;
1923 target-module@a000 { /* 0x4830a000, ap 100 60.0 */
1925 reg = <0xa000 0x4>,
1926 <0xa004 0x4>;
1937 clocks = <&l4ls_clkctrl AM4_L4LS_EPWMSS5_CLKCTRL 0>;
1941 ranges = <0x0 0xa000 0x1000>;
1943 epwmss5: epwmss@0 {
1945 reg = <0x0 0x10>;
1948 ranges = <0 0 0x1000>;
1956 reg = <0x200 0x80>;
1964 target-module@10000 { /* 0x48310000, ap 64 4e.1 */
1966 reg = <0x11fe0 0x4>,
1967 <0x11fe4 0x4>;
1973 clocks = <&l4ls_clkctrl AM4_L4LS_RNG_CLKCTRL 0>;
1977 ranges = <0x0 0x10000 0x2000>;
1979 rng: rng@0 {
1981 reg = <0x0 0x2000>;
1986 target-module@13000 { /* 0x48313000, ap 90 50.0 */
1991 ranges = <0x0 0x13000 0x1000>;
1994 target-module@18000 { /* 0x48318000, ap 62 4c.0 */
1999 ranges = <0x0 0x18000 0x4000>;
2002 target-module@20000 { /* 0x48320000, ap 82 34.0 */
2004 reg = <0x20000 0x4>,
2005 <0x20010 0x4>,
2006 <0x20114 0x4>;
2017 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO5_CLKCTRL 0>,
2022 ranges = <0x0 0x20000 0x1000>;
2024 gpio4: gpio@0 {
2026 reg = <0x0 0x1000>;
2036 target-module@22000 { /* 0x48322000, ap 116 64.0 */
2038 reg = <0x22000 0x4>,
2039 <0x22010 0x4>,
2040 <0x22114 0x4>;
2051 clocks = <&l4ls_clkctrl AM4_L4LS_GPIO6_CLKCTRL 0>,
2056 ranges = <0x0 0x22000 0x1000>;
2058 gpio5: gpio@0 {
2060 reg = <0x0 0x1000>;
2070 target-module@26000 { /* 0x48326000, ap 86 66.0 */
2072 reg = <0x26000 0x4>,
2073 <0x26104 0x4>;
2082 clocks = <&l3s_clkctrl AM4_L3S_VPFE0_CLKCTRL 0>;
2086 ranges = <0x0 0x26000 0x1000>;
2088 vpfe0: vpfe@0 {
2090 reg = <0x0 0x2000>;
2096 target-module@28000 { /* 0x48328000, ap 75 0e.0 */
2098 reg = <0x28000 0x4>,
2099 <0x28104 0x4>;
2108 clocks = <&l3s_clkctrl AM4_L3S_VPFE1_CLKCTRL 0>;
2112 ranges = <0x0 0x28000 0x1000>;
2114 vpfe1: vpfe@0 {
2116 reg = <0x0 0x2000>;
2122 target-module@2a000 { /* 0x4832a000, ap 88 3c.0 */
2124 reg = <0x2a000 0x4>,
2125 <0x2a010 0x4>,
2126 <0x2a014 0x4>;
2132 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2136 ranges = <0x00000000 0x0002a000 0x00000400>,
2137 <0x00000400 0x0002a400 0x00000400>,
2138 <0x00000800 0x0002a800 0x00000400>,
2139 <0x00000c00 0x0002ac00 0x00000400>,
2140 <0x00001000 0x0002b000 0x00001000>;
2142 dss: dss@0 {
2144 reg = <0 0x200>;
2150 ranges = <0x00000000 0x00000000 0x00000400>,
2151 <0x00000400 0x00000400 0x00000400>,
2152 <0x00000800 0x00000800 0x00000400>,
2153 <0x00000c00 0x00000c00 0x00000400>,
2154 <0x00001000 0x00001000 0x00001000>;
2158 reg = <0x400 0x4>,
2159 <0x410 0x4>,
2160 <0x414 0x4>;
2173 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2177 ranges = <0 0x400 0x400>;
2179 dispc: dispc@0 {
2181 reg = <0 0x400>;
2192 reg = <0x800 0x4>,
2193 <0x810 0x4>,
2194 <0x814 0x4>;
2202 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2206 ranges = <0 0x800 0x400>;
2208 rfbi: rfbi@0 {
2210 reg = <0 0x100>;
2211 clocks = <&dss_clkctrl AM4_DSS_DSS_CORE_CLKCTRL 0>;
2219 target-module@3d000 { /* 0x4833d000, ap 102 6e.0 */
2221 reg = <0x3d000 0x4>,
2222 <0x3d010 0x4>,
2223 <0x3d014 0x4>;
2231 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER9_CLKCTRL 0>;
2235 ranges = <0x0 0x3d000 0x1000>;
2237 timer9: timer@0 {
2239 reg = <0x0 0x400>;
2245 target-module@3f000 { /* 0x4833f000, ap 104 5c.0 */
2247 reg = <0x3f000 0x4>,
2248 <0x3f010 0x4>,
2249 <0x3f014 0x4>;
2257 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER10_CLKCTRL 0>;
2261 ranges = <0x0 0x3f000 0x1000>;
2263 timer10: timer@0 {
2265 reg = <0x0 0x400>;
2271 target-module@41000 { /* 0x48341000, ap 106 76.0 */
2273 reg = <0x41000 0x4>,
2274 <0x41010 0x4>,
2275 <0x41014 0x4>;
2283 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER11_CLKCTRL 0>;
2287 ranges = <0x0 0x41000 0x1000>;
2289 timer11: timer@0 {
2291 reg = <0x0 0x400>;
2297 target-module@45000 { /* 0x48345000, ap 108 6a.0 */
2299 reg = <0x45000 0x4>,
2300 <0x45110 0x4>,
2301 <0x45114 0x4>;
2311 clocks = <&l4ls_clkctrl AM4_L4LS_SPI4_CLKCTRL 0>;
2315 ranges = <0x0 0x45000 0x1000>;
2317 spi4: spi@0 {
2319 reg = <0x0 0x400>;
2322 #size-cells = <0>;
2327 target-module@47000 { /* 0x48347000, ap 110 70.0 */
2329 reg = <0x47000 0x4>,
2330 <0x47014 0x4>,
2331 <0x47018 0x4>;
2336 clocks = <&l4ls_clkctrl AM4_L4LS_HDQ1W_CLKCTRL 0>;
2340 ranges = <0x0 0x47000 0x1000>;
2342 hdq: hdq@0 {
2344 reg = <0x0 0x1000>;
2352 target-module@4c000 { /* 0x4834c000, ap 114 72.0 */
2357 ranges = <0x0 0x4c000 0x2000>;
2360 target-module@80000 { /* 0x48380000, ap 123 42.0 */
2362 reg = <0x80000 0x4>,
2363 <0x80010 0x4>;
2375 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS0_CLKCTRL 0>;
2379 ranges = <0x0 0x80000 0x20000>;
2381 dwc3_1: omap_dwc3@0 {
2383 reg = <0x0 0x10000>;
2388 ranges = <0 0 0x20000>;
2392 reg = <0x10000 0x10000>;
2410 target-module@a8000 { /* 0x483a8000, ap 125 6c.0 */
2412 reg = <0xa8000 0x4>;
2415 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP0_CLKCTRL 0>;
2419 ranges = <0x0 0xa8000 0x8000>;
2421 ocp2scp0: ocp2scp@0 {
2425 ranges = <0 0 0x8000>;
2429 reg = <0x0 0x8000>;
2430 syscon-phy-power = <&scm_conf 0x620>;
2434 #phy-cells = <0>;
2440 target-module@c0000 { /* 0x483c0000, ap 127 7a.0 */
2442 reg = <0xc0000 0x4>,
2443 <0xc0010 0x4>;
2455 clocks = <&l3s_clkctrl AM4_L3S_USB_OTG_SS1_CLKCTRL 0>;
2459 ranges = <0x0 0xc0000 0x20000>;
2461 dwc3_2: omap_dwc3@0 {
2463 reg = <0x0 0x10000>;
2468 ranges = <0 0 0x20000>;
2472 reg = <0x10000 0x10000>;
2490 target-module@e8000 { /* 0x483e8000, ap 129 78.0 */
2492 reg = <0xe8000 0x4>;
2495 clocks = <&l4ls_clkctrl AM4_L4LS_OCP2SCP1_CLKCTRL 0>;
2499 ranges = <0x0 0xe8000 0x8000>;
2501 ocp2scp1: ocp2scp@0 {
2505 ranges = <0 0 0x8000>;
2509 reg = <0x0 0x8000>;
2510 syscon-phy-power = <&scm_conf 0x628>;
2514 #phy-cells = <0>;
2520 target-module@f2000 { /* 0x483f2000, ap 112 5a.0 */
2525 ranges = <0x0 0xf2000 0x2000>;