Lines Matching +full:0 +full:x4c000000
23 memory@0 {
25 reg = <0 0>;
45 #size-cells = <0>;
46 cpu: cpu@0 {
50 reg = <0>;
79 opp-supported-hw = <0xFF 0x01>;
86 opp-supported-hw = <0xFF 0x04>;
92 opp-supported-hw = <0xFF 0x08>;
98 opp-supported-hw = <0xFF 0x10>;
104 opp-supported-hw = <0xFF 0x20>;
122 reg = <0x48241000 0x1000>,
123 <0x48240100 0x0100>;
131 reg = <0x48281000 0x1000>;
137 reg = <0x48240000 0x100>;
142 reg = <0x48240200 0x100>;
150 reg = <0x48240600 0x100>;
158 reg = <0x48242000 0x1000>;
170 reg = <0x44000000 0x400000
171 0x44800000 0x400000>;
178 reg = <0x100000 0x4000>,
179 <0x180000 0x2000>;
192 reg = <0x4c000000 0x1000000>;
202 reg = <0x49000000 0x4>;
204 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>;
208 ranges = <0x0 0x49000000 0x10000>;
210 edma: dma@0 {
212 reg = <0 0x10000>;
223 <&edma_tptc2 0>;
231 reg = <0x49800000 0x4>,
232 <0x49800010 0x4>;
238 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>;
242 ranges = <0x0 0x49800000 0x100000>;
244 edma_tptc0: dma@0 {
246 reg = <0 0x100000>;
254 reg = <0x49900000 0x4>,
255 <0x49900010 0x4>;
261 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>;
265 ranges = <0x0 0x49900000 0x100000>;
267 edma_tptc1: dma@0 {
269 reg = <0 0x100000>;
277 reg = <0x49a00000 0x4>,
278 <0x49a00010 0x4>;
284 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>;
288 ranges = <0x0 0x49a00000 0x100000>;
290 edma_tptc2: dma@0 {
292 reg = <0 0x100000>;
300 reg = <0x478102fc 0x4>,
301 <0x47810110 0x4>,
302 <0x47810114 0x4>;
312 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
316 ranges = <0x0 0x47810000 0x1000>;
318 mmc3: mmc@0 {
322 reg = <0x0 0x1000>;
329 reg = <0x53100100 0x4>,
330 <0x53100110 0x4>,
331 <0x53100114 0x4>;
340 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>;
344 ranges = <0x0 0x53100000 0x1000>;
346 sham: sham@0 {
348 reg = <0 0x300>;
349 dmas = <&edma 36 0>;
357 reg = <0x53501080 0x4>,
358 <0x53501084 0x4>,
359 <0x53501088 0x4>;
369 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>;
373 ranges = <0x0 0x53501000 0x1000>;
375 aes: aes@0 {
377 reg = <0 0xa0>;
379 dmas = <&edma 6 0>,
380 <&edma 5 0>;
387 reg = <0x53701030 0x4>,
388 <0x53701034 0x4>,
389 <0x53701038 0x4>;
399 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>;
403 ranges = <0 0x53701000 0x1000>;
405 des: des@0 {
407 reg = <0 0xa0>;
409 dmas = <&edma 34 0>,
410 <&edma 33 0>;
417 reg = <0x54426000 0x4>,
418 <0x54426004 0x4>;
428 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>;
434 ranges = <0x0 0x54400000 0x80000>;
440 dmas = <&edma 52 0>;
444 reg = <0x50000000 0x2000>;
459 reg = <0x47900000 0x4>,
460 <0x47900010 0x4>;
466 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>;
470 ranges = <0x0 0x47900000 0x1000>,
471 <0x30000000 0x30000000 0x4000000>;
473 qspi: spi@0 {
475 reg = <0 0x100>,
476 <0x30000000 0x4000000>;
481 #size-cells = <0>;
482 interrupts = <0 138 0x4>;
489 reg = <0x40300000 0x40000>; /* 256k */
490 ranges = <0x0 0x40300000 0x40000>;
494 pm_sram_code: pm-code-sram@0 {
496 reg = <0x0 0x1000>;
502 reg = <0x1000 0x1000>;
509 reg = <0x5600fe00 0x4>,
510 <0x5600fe10 0x4>;
518 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
521 resets = <&prm_gfx 0>;
525 ranges = <0 0x56000000 0x1000000>;
536 reg = <0x400 0x100>;
537 #power-domain-cells = <0>;
543 reg = <0x800 0x100>;
549 reg = <0x2000 0x100>;
555 reg = <0x4000 0x100>;
564 timer@0 {
574 timer@0 {