Lines Matching +full:0 +full:x4c000000
47 #size-cells = <0>;
48 cpu@0 {
52 reg = <0>;
86 opp-supported-hw = <0x06 0x0010>;
93 opp-supported-hw = <0x01 0x00FF>;
100 opp-supported-hw = <0x06 0x0020>;
107 opp-supported-hw = <0x01 0xFFFF>;
113 opp-supported-hw = <0x06 0x0040>;
119 opp-supported-hw = <0x01 0xFFFF>;
125 opp-supported-hw = <0x06 0x0080>;
131 opp-supported-hw = <0x01 0xFFFF>;
137 opp-supported-hw = <0x06 0x0100>;
143 opp-supported-hw = <0x04 0x0200>;
150 reg = <0x4b000000 0x1000000>;
185 reg = <0x100000 0x4000>,
186 <0x180000 0x2000>;
205 reg = <0x48200000 0x1000>;
210 reg = <0x49000000 0x4>;
212 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
216 ranges = <0x0 0x49000000 0x10000>;
218 edma: dma@0 {
220 reg = <0 0x10000>;
229 <&edma_tptc2 0>;
237 reg = <0x49800000 0x4>,
238 <0x49800010 0x4>;
244 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
248 ranges = <0x0 0x49800000 0x100000>;
250 edma_tptc0: dma@0 {
252 reg = <0 0x100000>;
260 reg = <0x49900000 0x4>,
261 <0x49900010 0x4>;
267 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
271 ranges = <0x0 0x49900000 0x100000>;
273 edma_tptc1: dma@0 {
275 reg = <0 0x100000>;
283 reg = <0x49a00000 0x4>,
284 <0x49a00010 0x4>;
290 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
294 ranges = <0x0 0x49a00000 0x100000>;
296 edma_tptc2: dma@0 {
298 reg = <0 0x100000>;
306 reg = <0x478102fc 0x4>,
307 <0x47810110 0x4>,
308 <0x47810114 0x4>;
318 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
322 ranges = <0x0 0x47810000 0x1000>;
324 mmc3: mmc@0 {
328 reg = <0x0 0x1000>;
335 reg = <0x47400000 0x4>,
336 <0x47400010 0x4>;
347 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
351 ranges = <0x0 0x47400000 0x8000>;
355 reg = <0x1300 0x100>;
358 #phy-cells = <0>;
363 reg = <0x1400 0x400>,
364 <0x1000 0x200>;
376 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
377 &cppi41dma 2 0 &cppi41dma 3 0
378 &cppi41dma 4 0 &cppi41dma 5 0
379 &cppi41dma 6 0 &cppi41dma 7 0
380 &cppi41dma 8 0 &cppi41dma 9 0
381 &cppi41dma 10 0 &cppi41dma 11 0
382 &cppi41dma 12 0 &cppi41dma 13 0
383 &cppi41dma 14 0 &cppi41dma 0 1
402 reg = <0x1b00 0x100>;
405 #phy-cells = <0>;
410 reg = <0x1c00 0x400>,
411 <0x1800 0x200>;
422 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
423 &cppi41dma 17 0 &cppi41dma 18 0
424 &cppi41dma 19 0 &cppi41dma 20 0
425 &cppi41dma 21 0 &cppi41dma 22 0
426 &cppi41dma 23 0 &cppi41dma 24 0
427 &cppi41dma 25 0 &cppi41dma 26 0
428 &cppi41dma 27 0 &cppi41dma 28 0
429 &cppi41dma 29 0 &cppi41dma 15 1
448 reg = <0x0000 0x1000>,
449 <0x2000 0x1000>,
450 <0x3000 0x1000>,
451 <0x4000 0x4000>;
463 reg = <0x40300000 0x10000>; /* 64k */
464 ranges = <0x0 0x40300000 0x10000>;
468 pm_sram_code: pm-code-sram@0 {
470 reg = <0x0 0x1000>;
476 reg = <0x1000 0x1000>;
483 reg = <0x4c000000 0x1000000>;
495 reg = <0x50000000 0x2000>;
497 dmas = <&edma 52 0>;
512 reg = <0x53100100 0x4>,
513 <0x53100110 0x4>,
514 <0x53100114 0x4>;
523 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
527 ranges = <0x0 0x53100000 0x1000>;
529 sham: sham@0 {
531 reg = <0 0x200>;
533 dmas = <&edma 36 0>;
540 reg = <0x53500080 0x4>,
541 <0x53500084 0x4>,
542 <0x53500088 0x4>;
552 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
556 ranges = <0x0 0x53500000 0x1000>;
558 aes: aes@0 {
560 reg = <0 0xa0>;
562 dmas = <&edma 6 0>,
563 <&edma 5 0>;
570 reg = <0x5600fe00 0x4>,
571 <0x5600fe10 0x4>;
579 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
582 resets = <&prm_gfx 0>;
586 ranges = <0 0x56000000 0x1000000>;
602 reg = <0xc00 0x100>;
608 reg = <0xd00 0x100>;
614 reg = <0xf00 0x100>;
620 reg = <0x1100 0x100>;
621 #power-domain-cells = <0>;
630 timer@0 {
640 timer@0 {