Lines Matching +full:4 +full:ns
136 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
145 gpmc,cs-on-ns = <0>;
146 gpmc,cs-rd-off-ns = <44>;
147 gpmc,cs-wr-off-ns = <44>;
148 gpmc,adv-on-ns = <6>;
149 gpmc,adv-rd-off-ns = <34>;
150 gpmc,adv-wr-off-ns = <44>;
151 gpmc,we-on-ns = <0>;
152 gpmc,we-off-ns = <40>;
153 gpmc,oe-on-ns = <0>;
154 gpmc,oe-off-ns = <54>;
155 gpmc,access-ns = <64>;
156 gpmc,rd-cycle-ns = <82>;
157 gpmc,wr-cycle-ns = <82>;
158 gpmc,bus-turnaround-ns = <0>;
159 gpmc,cycle2cycle-delay-ns = <0>;
160 gpmc,clk-activation-ns = <0>;
161 gpmc,wr-access-ns = <40>;
162 gpmc,wr-data-mux-bus-ns = <0>;
189 partition@4 {
211 bus-width = <4>;
246 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
255 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
263 vdd3_reg: regulator@4 {