Lines Matching refs:c0
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
683 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
722 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
723 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
724 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
727 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
728 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
734 mrc p15, 0, r0, c1, c0, 0 @ read control reg
739 mcr p15, 0, r0, c1, c0, 0 @ write control reg
751 mcr p15, 0, r0, c2, c0, 0 @ cache on
752 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
755 mcr p15, 0, r0, c5, c0, 0 @ access permission
758 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
763 mrc p15, 0, r0, c1, c0, 0 @ read control reg
768 mcr p15, 0, r0, c1, c0, 0 @ write control reg
771 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
824 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
827 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
833 mcr p15, 7, r0, c15, c0, 0
844 mrc p15, 0, r0, c1, c0, 0 @ read control reg
858 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
867 mrc p15, 0, r0, c1, c0, 0 @ read control reg
876 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
881 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
882 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
883 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
886 mcr p15, 0, r0, c1, c0, 0 @ load control register
887 mrc p15, 0, r0, c1, c0, 0 @ and read it back
900 mrc p15, 0, r0, c1, c0, 0 @ read control reg
913 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
914 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
917 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
918 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
940 mrc p15, 0, r9, c0, c0 @ get processor ID
1147 mrc p15, 0, r0, c1, c0
1149 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1157 mrc p15, 0, r0, c1, c0
1159 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1161 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1166 mrc p15, 0, r0, c1, c0
1168 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1176 mrc p15, 0, r0, c1, c0
1182 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1250 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1288 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1322 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1433 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1435 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1464 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR