Lines Matching refs:erratum

851 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
860 	  r1p* erratum. If a code sequence containing an ARM/Thumb
877 	  erratum. For very specific sequences of memory operations, it is
891 	  erratum. Any asynchronous access to the L2 cache may encounter a
904 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
917 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
932 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
942 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
944 	  As a consequence of this erratum, some TLB entries which should be
955 	  (r2p*) erratum. Under very rare conditions, a faulty
969 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
979 	  r3p*) erratum. A speculative memory access may cause a page table walk
990 	  r2p0) erratum. The Store Buffer does not have any automatic draining
1001 	  r0p2 erratum (possible cache data corruption with
1012 	  This option enables the workaround for erratum 764369
1027 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
1038 	  option enables the Linux kernel workaround for this erratum
1047 	  (up to r0p4) erratum. In certain rare sequences of code, the
1049 	  workaround disables the loop buffer to avoid the erratum.
1070 	  (all revs) erratum. In very rare timing conditions, a sequence
1080 	  (all revs) erratum. Within rare timing constraints, executing a
1089 	  (all revs) erratum. Under very rare timing conditions, the CPU might
1097 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1109 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1110 	  config option from the A12 erratum due to the way errata are checked
1117 	  This option enables the workaround for the 857272 Cortex-A17 erratum.
1118 	  This erratum is not known to be fixed in any A17 revision.
1119 	  This is identical to Cortex-A12 erratum 857271.  It is a separate
1120 	  config option from the A12 erratum due to the way errata are checked
1160 	  However, because of this erratum, an L2 set/way cache maintenance