Lines Matching +full:cortex +full:- +full:a15 +full:- +full:timer
1 # SPDX-License-Identifier: GPL-2.0
129 The ARM series is a line of low-power-consumption RISC chip designs
131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
132 manufactured, but legacy ARM-based PC hardware remains popular in
242 Patch phys-to-virt and virt-to-phys translation functions at
246 This can only be used with non-XIP MMU kernels where the base
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
347 bool "EBSA-110"
356 from Digital. It has limited hardware on-board, including an
361 bool "EP93xx-based"
389 bool "IOP32x-based"
402 bool "IXP4xx-based"
438 bool "PXA2xx/PXA3xx-based"
475 On the Acorn Risc-PC, Linux can support the internal IDE disk and
476 CD-ROM interface, serial and parallel port, and the floppy drive.
479 bool "SA1100-based"
578 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
607 # This is sorted alphabetically by mach-* pathname. However, plat-*
609 # plat- suffix) or along side the corresponding mach-* source.
611 source "arch/arm/mach-actions/Kconfig"
613 source "arch/arm/mach-alpine/Kconfig"
615 source "arch/arm/mach-artpec/Kconfig"
617 source "arch/arm/mach-asm9260/Kconfig"
619 source "arch/arm/mach-aspeed/Kconfig"
621 source "arch/arm/mach-at91/Kconfig"
623 source "arch/arm/mach-axxia/Kconfig"
625 source "arch/arm/mach-bcm/Kconfig"
627 source "arch/arm/mach-berlin/Kconfig"
629 source "arch/arm/mach-clps711x/Kconfig"
631 source "arch/arm/mach-cns3xxx/Kconfig"
633 source "arch/arm/mach-davinci/Kconfig"
635 source "arch/arm/mach-digicolor/Kconfig"
637 source "arch/arm/mach-dove/Kconfig"
639 source "arch/arm/mach-ep93xx/Kconfig"
641 source "arch/arm/mach-exynos/Kconfig"
643 source "arch/arm/mach-footbridge/Kconfig"
645 source "arch/arm/mach-gemini/Kconfig"
647 source "arch/arm/mach-highbank/Kconfig"
649 source "arch/arm/mach-hisi/Kconfig"
651 source "arch/arm/mach-imx/Kconfig"
653 source "arch/arm/mach-integrator/Kconfig"
655 source "arch/arm/mach-iop32x/Kconfig"
657 source "arch/arm/mach-ixp4xx/Kconfig"
659 source "arch/arm/mach-keystone/Kconfig"
661 source "arch/arm/mach-lpc32xx/Kconfig"
663 source "arch/arm/mach-mediatek/Kconfig"
665 source "arch/arm/mach-meson/Kconfig"
667 source "arch/arm/mach-milbeaut/Kconfig"
669 source "arch/arm/mach-mmp/Kconfig"
671 source "arch/arm/mach-moxart/Kconfig"
673 source "arch/arm/mach-mstar/Kconfig"
675 source "arch/arm/mach-mv78xx0/Kconfig"
677 source "arch/arm/mach-mvebu/Kconfig"
679 source "arch/arm/mach-mxs/Kconfig"
681 source "arch/arm/mach-nomadik/Kconfig"
683 source "arch/arm/mach-npcm/Kconfig"
685 source "arch/arm/mach-nspire/Kconfig"
687 source "arch/arm/plat-omap/Kconfig"
689 source "arch/arm/mach-omap1/Kconfig"
691 source "arch/arm/mach-omap2/Kconfig"
693 source "arch/arm/mach-orion5x/Kconfig"
695 source "arch/arm/mach-oxnas/Kconfig"
697 source "arch/arm/mach-picoxcell/Kconfig"
699 source "arch/arm/mach-prima2/Kconfig"
701 source "arch/arm/mach-pxa/Kconfig"
702 source "arch/arm/plat-pxa/Kconfig"
704 source "arch/arm/mach-qcom/Kconfig"
706 source "arch/arm/mach-rda/Kconfig"
708 source "arch/arm/mach-realtek/Kconfig"
710 source "arch/arm/mach-realview/Kconfig"
712 source "arch/arm/mach-rockchip/Kconfig"
714 source "arch/arm/mach-s3c/Kconfig"
716 source "arch/arm/mach-s5pv210/Kconfig"
718 source "arch/arm/mach-sa1100/Kconfig"
720 source "arch/arm/mach-shmobile/Kconfig"
722 source "arch/arm/mach-socfpga/Kconfig"
724 source "arch/arm/mach-spear/Kconfig"
726 source "arch/arm/mach-sti/Kconfig"
728 source "arch/arm/mach-stm32/Kconfig"
730 source "arch/arm/mach-sunxi/Kconfig"
732 source "arch/arm/mach-tango/Kconfig"
734 source "arch/arm/mach-tegra/Kconfig"
736 source "arch/arm/mach-u300/Kconfig"
738 source "arch/arm/mach-uniphier/Kconfig"
740 source "arch/arm/mach-ux500/Kconfig"
742 source "arch/arm/mach-versatile/Kconfig"
744 source "arch/arm/mach-vexpress/Kconfig"
746 source "arch/arm/mach-vt8500/Kconfig"
748 source "arch/arm/mach-zx/Kconfig"
750 source "arch/arm/mach-zynq/Kconfig"
752 # ARMv7-M architecture
769 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
778 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
779 with a range of available cores like Cortex-M3/M4/M7.
820 source "arch/arm/Kconfig-nommu"
838 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
841 Executing a SWP instruction to read-only memory does not set bit 11
859 This option enables the workaround for the 430973 Cortex-A8
862 same virtual address, whether due to self-modifying code or virtual
863 to physical address re-mapping, Cortex-A8 does not recover from the
864 stale interworking branch prediction. This results in Cortex-A8
869 available in non-secure mode.
876 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
883 register may not be available in non-secure mode.
890 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
894 workaround disables the write-allocate mode for the L2 cache via the
896 may not be available in non-secure mode.
903 This option enables the workaround for the 742230 Cortex-A9
907 the diagnostic register of the Cortex-A9 which causes the DMB
916 This option enables the workaround for the 742231 Cortex-A9
918 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
923 register of the Cortex-A9 which reduces the linefill issuing
931 This option enables the workaround for the 643719 Cortex-A9 (prior to
941 This option enables the workaround for the 720789 Cortex-A9 (prior to
954 This option enables the workaround for the 743622 Cortex-A9
956 optimisation in the Cortex-A9 Store Buffer may lead to data
958 register of the Cortex-A9 which disables the Store Buffer
968 This option enables the workaround for the 751472 Cortex-A9 (prior
978 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
981 can populate the micro-TLB with a stale entry which may be hit with
989 This option enables the workaround for the 754327 Cortex-A9 (prior to
997 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1002 hit-under-miss enabled). It sets the undocumented bit 31 in
1004 register, thus disabling hit-under-miss without putting the
1013 affecting Cortex-A9 MPCore with two or more processors (all
1026 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1033 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1036 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1046 This option enables the workaround for the 773022 Cortex-A15
1056 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1058 - Cortex-A12 852422: Execution of a sequence of instructions might
1060 any Cortex-A12 cores yet.
1069 This option enables the workaround for the 821420 Cortex-A12
1073 deadlock when the VMOV instructions are issued out-of-order.
1079 This option enables the workaround for the 825619 Cortex-A12
1082 and Device/Strongly-Ordered loads and stores might cause deadlock
1088 This option enables the workaround for the 857271 Cortex-A12
1096 This option enables the workaround for the 852421 Cortex-A17
1106 - Cortex-A17 852423: Execution of a sequence of instructions might
1108 any Cortex-A17 cores yet.
1109 This is identical to Cortex-A12 erratum 852422. It is a separate
1117 This option enables the workaround for the 857272 Cortex-A17 erratum.
1119 This is identical to Cortex-A12 erratum 857271. It is a separate
1162 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1172 This option should be selected by machines which have an SMP-
1175 The only effect of this option is to make the SMP-related
1179 bool "Symmetric Multi-Processing"
1190 If you say N here, the kernel will run on uni- and multiprocessor
1196 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1197 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1198 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1207 SMP kernels contain instructions which fail on non-SMP processors.
1224 bool "Multi-core scheduler support"
1227 Multi-core scheduler support improves the CPU scheduler's decision
1228 making when dealing with multi-core CPU chips at a cost of slightly
1245 bool "Architected timer support"
1249 This option enables support for the ARM architected timer
1254 This options enables support for the ARM timer and watchdog unit
1257 bool "Multi-Cluster Power Management"
1261 for (multi-)cluster based systems, such as big.LITTLE based
1287 transparently handle transition between a cluster of A15's
1328 int "Maximum number of CPUs (2-32)"
1334 bool "Support for hot-pluggable CPUs"
1347 implementing the PSCI specification for CPU-centric power
1381 prompt "Timer frequency"
1417 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1423 Thumb-2 mode.
1517 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1525 user-space 2nd level page tables to reside in high memory.
1528 bool "Enable use of CPU domains to implement privileged no-access"
1534 use-after-free bugs becoming an exploitable privilege escalation
1538 CPUs with low-vector mappings use a best-efforts implementation.
1571 Disabling this is usually safe for small single-platform
1598 address divisible by 4. On 32-bit ARM processors, these non-aligned
1601 correct operation of some network protocols. With an IP-only
1610 cores where a 8-word STM instruction give significantly higher
1617 However, if the CPU data cache is using a write-allocate mode,
1705 The physical address at which the ROM-able zImage is to be
1707 ROM-able zImage formats normally set this to a suitable
1717 for the ROM-able zImage which must be available while the
1720 Platforms which normally make use of ROM-able zImage formats
1772 Uses the command-line options passed by the boot loader instead of
1779 The command-line arguments provided by the boot loader will be
1790 architectures, you should supply some command-line options at build
1802 Uses the command-line options passed by the boot loader. If
1809 The command-line arguments provided by the boot loader will be
1818 command-line options your boot loader passes to the kernel.
1822 bool "Kernel Execute-In-Place from ROM"
1825 Execute-In-Place allows the kernel to run from non-volatile storage
1828 to RAM. Read-write sections, such as the data section and stack,
1890 loaded in the main kernel with kexec-tools into a specially
1895 For more details see Documentation/admin-guide/kdump/kdump.rst
1902 will be determined at run-time by masking the current IP with
1919 by UEFI firmware (such as non-volatile variables, realtime
1934 continue to boot on existing non-UEFI platforms.
1940 to be enabled much earlier than we do on ARM, which is non-trivial.
1963 your machine has an FPA or floating point co-processor podule.
1972 Say Y to include 80-bit support in the kernel floating-point
1973 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1974 Note that gcc does not generate 80-bit operations by default,
1987 It is very simple, and approximately 3-6 times faster than NWFPE.
1995 bool "VFP-format floating point maths"
2001 Please see <file:Documentation/arm/vfp/release-notes.rst> for