Lines Matching full:mb
45 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
56 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
95 char mb[32]; in axs10x_early_init() local
105 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
106 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
122 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
123 * of which maps to a corresponding 256MB aperture in Target slave memory map.
128 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
132 * MB AXI Tunnel Master, which also has a mem map setup
134 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
135 * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
149 /* MB AXI Target slaves */
156 /* MB AXI masters */
178 {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */
183 * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
184 * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
206 * memmap for MB AXI Masters
207 * Same mem map for all perip controllers as well as MB AXI Tunnel Master
224 {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */
261 /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ in axs101_early_init()
266 /* MB peripherals memory map */ in axs101_early_init()
276 /* Set up the MB interrupt system: mux interrupts to GPIO7) */ in axs101_early_init()
282 /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */ in axs101_early_init()