18  *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
21  * vineetg: April 2011 : Preparing for MMU V3
22  *  -MMU v2/v3 BCRs decoded differently
27  *      = walks MMU only if range spans < 32 entries, as opposed to 256
30  *  -Changes related to MMU v2 (Rel 4.8)
33  *  -In TLB Flush operations (Metal Fix MMU) there is a explicit command to
58 #include <asm/mmu.h>
60 /*			Need for ARC MMU v2
62  * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
126 	/* MMU v2 introduced the uTLB Flush command.  in utlb_invalidate()
129 	 * return lkup err - because the entry didn't exist in MMU.  in utlb_invalidate()
131 	 * flush. This was fixed in MMU v3  in utlb_invalidate()
190 	 * If Not already present get a free slot from MMU.  in tlb_entry_insert()
202 	 * Commit the Entry to MMU  in tlb_entry_insert()
231  * Un-conditionally (without lookup) erase the entire MMU contents
236 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in local_flush_tlb_all()  local
239 	int num_tlb = mmu->sets * mmu->ways;  in local_flush_tlb_all()
282 	 * Only for fork( ) do we need to move parent to a new MMU ctxt,  in local_flush_tlb_mm()
345 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
374  * Delete TLB entry in MMU for a given page (??? address)
503 	 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)  in create_tlb()
507 	 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.  in create_tlb()
546 	 * ARC MMU provides fully orthogonal access bits for K/U mode,  in create_tlb()
548 	 * Here we convert 3 PTE bits into 6 MMU bits:  in create_tlb()
568  *  -pre-install the corresponding TLB entry into MMU
624  *  - MMU page size (typical 8K, RTL fixed)
707 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in read_decode_mmu_bcr()  local
739 	mmu->ver = (tmp >> 24);  in read_decode_mmu_bcr()
742 		if (mmu->ver <= 2) {  in read_decode_mmu_bcr()
744 			mmu->pg_sz_k = TO_KB(0x2000);  in read_decode_mmu_bcr()
745 			mmu->sets = 1 << mmu2->sets;  in read_decode_mmu_bcr()
746 			mmu->ways = 1 << mmu2->ways;  in read_decode_mmu_bcr()
747 			mmu->u_dtlb = mmu2->u_dtlb;  in read_decode_mmu_bcr()
748 			mmu->u_itlb = mmu2->u_itlb;  in read_decode_mmu_bcr()
751 			mmu->pg_sz_k = 1 << (mmu3->pg_sz - 1);  in read_decode_mmu_bcr()
752 			mmu->sets = 1 << mmu3->sets;  in read_decode_mmu_bcr()
753 			mmu->ways = 1 << mmu3->ways;  in read_decode_mmu_bcr()
754 			mmu->u_dtlb = mmu3->u_dtlb;  in read_decode_mmu_bcr()
755 			mmu->u_itlb = mmu3->u_itlb;  in read_decode_mmu_bcr()
756 			mmu->sasid = mmu3->sasid;  in read_decode_mmu_bcr()
760 		mmu->pg_sz_k = 1 << (mmu4->sz0 - 1);  in read_decode_mmu_bcr()
761 		mmu->s_pg_sz_m = 1 << (mmu4->sz1 - 11);  in read_decode_mmu_bcr()
762 		mmu->sets = 64 << mmu4->n_entry;  in read_decode_mmu_bcr()
763 		mmu->ways = mmu4->n_ways * 2;  in read_decode_mmu_bcr()
764 		mmu->u_dtlb = mmu4->u_dtlb * 4;  in read_decode_mmu_bcr()
765 		mmu->u_itlb = mmu4->u_itlb * 4;  in read_decode_mmu_bcr()
766 		mmu->sasid = mmu4->sasid;  in read_decode_mmu_bcr()
767 		pae_exists = mmu->pae = mmu4->pae;  in read_decode_mmu_bcr()
774 	struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;  in arc_mmu_mumbojumbo()
783 		      "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",  in arc_mmu_mumbojumbo()
799 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in arc_mmu_init()  local
817 	 * Ensure that MMU features assumed by kernel exist in hardware.  in arc_mmu_init()
818 	 * For older ARC700 cpus, it has to be exact match, since the MMU  in arc_mmu_init()
825 	if (is_isa_arcompact() && mmu->ver == CONFIG_ARC_MMU_VER)  in arc_mmu_init()
827 	else if (is_isa_arcv2() && mmu->ver >= CONFIG_ARC_MMU_VER)  in arc_mmu_init()
831 		panic("MMU ver %d doesn't match kernel built for %d...\n",  in arc_mmu_init()
832 		      mmu->ver, CONFIG_ARC_MMU_VER);  in arc_mmu_init()
835 	if (mmu->pg_sz_k != TO_KB(PAGE_SIZE))  in arc_mmu_init()
836 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));  in arc_mmu_init()
839 	    mmu->s_pg_sz_m != TO_MB(HPAGE_PMD_SIZE))  in arc_mmu_init()
840 		panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n",  in arc_mmu_init()
843 	if (IS_ENABLED(CONFIG_ARC_HAS_PAE40) && !mmu->pae)  in arc_mmu_init()
846 	/* Enable the MMU */  in arc_mmu_init()
871  * MMU cmd getIndex(vaddr) abstracts that out.
874 #define SET_WAY_TO_IDX(mmu, set, way)  ((set) * mmu->ways + (way))  argument
876 /* Handling of Duplicate PD (TLB entry) in MMU.
878  * -MMU complaints not at the time of duplicate PD installation, but at the
889 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;  in do_tlb_overlap_fault()  local
891 	int set, n_ways = mmu->ways;  in do_tlb_overlap_fault()
894 	BUG_ON(mmu->ways > 4);  in do_tlb_overlap_fault()
899 	for (set = 0; set < mmu->sets; set++) {  in do_tlb_overlap_fault()
907 					  SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()
940 						SET_WAY_TO_IDX(mmu, set, way));  in do_tlb_overlap_fault()