109 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_read_counter()
111 	write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);  in arc_pmu_read_counter()
232 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);  in arc_pmu_enable()
240 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);  in arc_pmu_disable()
273 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_event_set_period()
276 	write_aux_reg(ARC_REG_PCT_COUNTL, lower_32_bits(value));  in arc_pmu_event_set_period()
277 	write_aux_reg(ARC_REG_PCT_COUNTH, upper_32_bits(value));  in arc_pmu_event_set_period()
306 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_start()
310 	write_aux_reg(ARC_REG_PCT_INDEX, idx);		/* counter # */  in arc_pmu_start()
311 	write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);	/* condition */  in arc_pmu_start()
325 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));  in arc_pmu_stop()
326 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_stop()
332 		write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_stop()
335 		write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_stop()
373 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_add()
379 		write_aux_reg(ARC_REG_PCT_INT_CNTL,  in arc_pmu_add()
381 		write_aux_reg(ARC_REG_PCT_INT_CNTH,  in arc_pmu_add()
385 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_add()
386 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);  in arc_pmu_add()
387 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);  in arc_pmu_add()
423 		write_aux_reg(ARC_REG_PCT_INT_ACT, BIT(idx));  in arc_pmu_intr()
430 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_intr()
469 	write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);  in arc_cpu_pmu_irq_init()
616 		write_aux_reg(ARC_REG_CC_INDEX, i);  in arc_pmu_device_probe()