62 #define clear_irq_work_pending()     __this_cpu_write(irq_work_pending, 0)
71 #define test_irq_work_pending()      0
129 	clockevents_config_and_register(ce, CONFIG_HZ, 0, 0);  in init_rtc_clockevent()
161 	qemu_set_alarm_abs(0);  in qemu_ce_shutdown()
162 	return 0;  in qemu_ce_shutdown()
169 	return 0;  in qemu_ce_set_next_event()
206 	unsigned char x, sel = 0;  in common_init_rtc()
210  	x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;  in common_init_rtc()
212 	   where 0x26 is wrong; we refuse to change those. */  in common_init_rtc()
213  	if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {  in common_init_rtc()
237 	outb(0x36, 0x43);	/* pit counter 0: system timer */  in common_init_rtc()
238 	outb(0x00, 0x40);  in common_init_rtc()
239 	outb(0x00, 0x40);  in common_init_rtc()
241 	outb(0xb6, 0x43);	/* pit counter 2: speaker */  in common_init_rtc()
242 	outb(0x31, 0x42);  in common_init_rtc()
243 	outb(0x13, 0x42);  in common_init_rtc()
283    Return 0 if the result cannot be trusted, otherwise return the argument.  */
317 	index = cpu->type & 0xffffffff;  in validate_cc_value()
324 	if (cpu_hz[index].max == 0)  in validate_cc_value()
329 		return 0;  in validate_cc_value()
340 #define CALIBRATE_LATCH	0xffff
341 #define TIMEOUT_COUNT	0x100000
346 	int cc, count = 0;  in calibrate_cc_with_pit()
349 	outb((inb(0x61) & ~0x02) | 0x01, 0x61);  in calibrate_cc_with_pit()
354 	 * Set the Gate high, program CTC channel 2 for mode 0,  in calibrate_cc_with_pit()
358 	outb(0xb0, 0x43);		/* binary, mode 0, LSB/MSB, Ch 2 */  in calibrate_cc_with_pit()
359 	outb(CALIBRATE_LATCH & 0xff, 0x42);	/* LSB of count */  in calibrate_cc_with_pit()
360 	outb(CALIBRATE_LATCH >> 8, 0x42);	/* MSB of count */  in calibrate_cc_with_pit()
365 	} while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);  in calibrate_cc_with_pit()
370 		return 0;  in calibrate_cc_with_pit()
376    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
423 		if (diff < 0)  in time_init()
430 			est_cycle_freq = 0;  in time_init()