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1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
23 time introduces a new set of challenges because it introduces a multiplexed
24 division of time beyond the control of the guest CPU.
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
63 -------------- | +->| GATE TIMER 0 |
64 | ----------------
66 | ----------------
68 |------>| CLOCK OUT | ---------> 66.3 KHZ DRAM
70 | +->| GATE TIMER 1 |
71 | ----------------
73 | ----------------
75 |------>| CLOCK OUT | ---------> Port 61h, bit 5
77 Port 61h, bit 0 -------->| GATE TIMER 2 | \_.---- ____
78 ---------------- _| )--|LPF|---Speaker
79 / *---- \___/
80 Port 61h, bit 1 ---------------------------------/
85 This is a one-shot software timeout that counts down
89 Mode 1: Triggered One-shot.
110 for (N-1)/2 counts. Only even values are latched by the counter, so odd
112 which generates sine-like tones by low-pass filtering the square wave output.
133 Bit 7-4: Command (See table below)
134 Bit 3-1: Mode (000 = Mode 0, 101 = Mode 5, 11X = undefined)
139 0000 - Latch Timer 0 count for port 0x40
144 0001 - Set Timer 0 LSB mode for port 0x40
148 0010 - Set Timer 0 MSB mode for port 0x40
152 0011 - Set Timer 0 16-bit mode for port 0x40
156 0100 - Latch Timer 1 count for port 0x41 - as described above
157 0101 - Set Timer 1 LSB mode for port 0x41 - as described above
158 0110 - Set Timer 1 MSB mode for port 0x41 - as described above
159 0111 - Set Timer 1 16-bit mode for port 0x41 - as described above
161 1000 - Latch Timer 2 count for port 0x42 - as described above
162 1001 - Set Timer 2 LSB mode for port 0x42 - as described above
163 1010 - Set Timer 2 MSB mode for port 0x42 - as described above
164 1011 - Set Timer 2 16-bit mode for port 0x42 as described above
166 1101 - General counter latch
173 1110 - Latch timer status
179 The output of ports 0x40-0x42 following this command will be:
183 Bit 5-4 = Read / Write mode
186 11 = LSB / MSB (16-bit)
187 Bit 3-1 = Mode
191 --------
194 time clock. The original device is now obsolete, and usually emulated by the
208 The RTC will update the current time fields by battery power even while the
209 system is off. The current time fields should not be read while an update is
212 The clock uses a 32.768kHz crystal, so bits 6-4 of register A should be
218 ------------------------------------------
231 bit 6-4 = Divider for clock
238 bit 3-0 = Rate selection for periodic interrupt
252 bit 4 = Update-ended interrupt enable
255 bit 1 = 12-hour mode (0) / 24-hour mode (1)
262 bit 3-0 = reserved
264 bit 7 = RTC has power
265 bit 6-0 = reserved
270 ---------
272 On Pentium and later processors, an on-board timer is available to each CPU
274 accessed through memory-mapped registers and provides interrupt service to each
277 Although in theory the APIC is a safe and stable source for local interrupts,
279 the APIC CPU-local memory-mapped hardware. Beware that CPU errata may affect
281 these workarounds pose unique constraints for virtualization - requiring either
282 extra overhead incurred from extra reads of memory-mapped I/O or additional
288 of one-shot or periodic operation, and is based on the bus clock divided down
292 ---------
306 time source which is independent of local variation (as there is only one HPET
307 in any given system). The HPET is also memory-mapped, and its presence is
314 --------------------
322 not considered important at this time as no known operating system does this.
327 The TSC or time stamp counter is relatively simple in theory; it counts
329 time. In practice, due to a number of problems, it is the most complicated
332 The TSC is represented internally as a 64-bit MSR which can be read with the
335 was only possible to write the low 32-bits of the 64-bit counter, and the upper
336 32-bits of the counter were cleared. Now, however, on Intel processors family
338 has been lifted and all 64-bits are writable. On AMD systems, the ability to
341 The TSC is accessible from CPL-0 and conditionally, for CPL > 0 software by
357 ------------------------
359 The TSC is a CPU-local clock in most implementations. This means, on SMP
366 Several hardware limitations make the problem worse - if it is not possible to
367 write the full 64-bits of the TSC, it may be impossible to match the TSC in
375 ------------------------
377 As touched on already, CPUs which arrive later than the boot time of the system
385 3.3. TSC and multi-socket / NUMA
386 --------------------------------
388 Multi-socket systems, especially large multi-socket systems are likely to have
392 cause the CPU clocks, and thus the TSCs to drift over time. Depending on the
394 error, and may accumulate over time.
397 cores. This technique, known as spread-spectrum clocking, reduces EMI at the
404 3.4. TSC and C-states
405 ---------------------
407 C-states, or idling states of the processor, especially C1E and deeper sleep
416 3.5. TSC frequency change / P-states
417 ------------------------------------
421 may be staggered or slewed, at some points in time, the TSC rate may not be
423 not be a stable time source, and must be calibrated against a known, stable,
424 external clock to be a usable source of time.
426 Whether the TSC runs at a constant rate or scales with the P-state is model
430 In addition, some vendors have known bugs where the P-state is actually
432 inactive, the P-state may be raised temporarily to service cache misses from
434 than that of non-halted processors. AMD Turion processors are known to have
437 3.6. TSC and STPCLK / T-states
438 ------------------------------
441 the TSC. This is typically done for thermal emergency power control to prevent
445 3.7. TSC virtualization - VMX
446 -----------------------------
454 3.8. TSC virtualization - SVM
455 -----------------------------
463 ------------------------------
467 if so, the TSCs in multi-sockets or NUMA systems may still run independently
476 X86_FEATURE_CONSTANT_TSC The TSC rate is unchanged with P-states
477 X86_FEATURE_NONSTOP_TSC The TSC does not stop in C-states
485 challenges arise. The most obvious problem is that time is now shared between
491 at any time. This causes problems as the passage of real time, the injection
493 synchronized with real time.
502 -----------------------
506 time by counting periodic interrupts. These interrupts may come from the PIT
509 time may fall behind. This is especially problematic if a high interrupt rate
514 to simply ignore it. Guests which have a separate time source for tracking
515 'wall clock' or 'real time' may not need any adjustment of their interrupts to
516 maintain proper time. If this is not sufficient, it may be necessary to inject
526 Windows uses periodic RTC clocking as a means of keeping time internally, and
527 thus requires interrupt slewing to keep proper time. It does use a low enough
532 -----------------------------------
534 As the highest precision time source available, the cycle counter of the CPU
543 non-serialized. Forcing serialized execution is necessary for precise
549 accurate time stamp counter reading may therefore not always be available, and
555 ----------------------
558 when using results of the TSC when measured against another time source. As
563 Due to non-serialized reads, you may actually end up with a range which
564 fluctuates - from (T-1.. T+10). Thus, any time calculated from a TSC, but
566 Re-calibrating this computation may actually cause time, as computed after the
567 calibration, to go backwards, compared with time computed before the
570 This problem is particularly pronounced with an internal time source in Linux,
571 the kernel time, which is expressed in the theoretically high resolution
572 timespec - but which advances in much larger granularity intervals, sometimes
580 --------------
583 First, the migration itself may take time, during which interrupts cannot be
584 delivered, and after which, the guest time may need to be caught up. NTP may
586 typically small enough to fall in the NTP-correctable window.
592 faster clock cannot be made visible to a guest without the potential of time
599 ---------------
609 paravirtualized scheduler clock, which reveals the true amount of CPU time for
613 --------------
617 misinterpretation of the passage of real time. Usually, these warnings are
622 --------------------------------
628 adequately virtualized without a full real-time operating system, which would
636 ------------------------------
638 In addition to the above problems, time information will inevitably leak to the
640 time. This may allow the guest to infer the presence of a hypervisor (as in a
641 red-pill type detection), and it may allow information to leak between guests
643 problems would require completely isolated virtual time which may not track
644 real time any longer. This may be useful in certain security or QA contexts,
645 but in general isn't recommended for real-world deployment scenarios.