Lines Matching +full:retain +full:- +full:state +full:- +full:suspended

47 Between these points the processor is in 'Transactional' state; any memory
49 transactional or non-transactional accesses within the system.  In this
50 example, the transaction completes as though it were normal straight-line code
59 state will roll back to that at the 'tbegin', and control will continue from
69 - Conflicts with cache lines used by other processors
70 - Signals
71 - Context switches
72 - See the ISA for full documentation of everything that will abort transactions.
82 Syscalls made from within a suspended transaction are performed as normal and
85 by the hardware.  The syscall is performed in suspended mode so any side
101 thread state (ucontext/mcontext) to represent the second transactional register
102 state.  Signal delivery 'treclaim's to capture both register states, so signals
104 represents the checkpointed/original register state; the signal appears to have
109 determine the transactional state -- if so, the second ucontext in uc->uc_link
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
117 uc->uc_link->uc_mcontext.regs->msr.  The top word contains the transactional
118 state TS.
123 Transaction-aware signal handlers can read the transactional register state
132       ucontext_t *transactional_ucp = ucp->uc_link;
135         u64 msr = ucp->uc_mcontext.regs->msr;
138         msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32;
144                            ucp->uc_mcontext.regs->nip,
145                            transactional_ucp->uc_mcontext.regs->nip);
149       fix_the_problem(ucp->dar);
156 transactional memory state.  If we write over this non transactionally or in
162 the stack pointer from the checkpointed state, rather than the speculated
163 state.  This ensures that the signal context (written tm suspended) will be
168 For signals taken in non-TM or suspended mode, we use the
169 normal/non-checkpointed stack pointer.
171 Any transaction initiated inside a sighandler and suspended on return
198 GDB and ptrace are not currently TM-aware.  If one stops during a transaction,
199 it looks like the transaction has just started (the checkpointed state is
201 handler route.  Furthermore, the transactional 2nd register state will be
208 TM on POWER9 has issues with storing the complete register state. This
253 -------------------
258 off but TM suspended). Regularly the kernel will want change bits in
261 resulting MSR will retain TM = 0 and TS=01 from before (ie. stay in
263 be a transition from TS=01 to TS=00 (ie. suspend -> non transactional)
270      MSR 29:31 <- SRR1 29:31