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28 There is thus, in HW, a table of PE states that contains a pair of "frozen"
33 return all 1's value. MSIs are also blocked. There's a bit more state that
66       bridge being triggered.  There's a PE# in the interrupt controller
75     from the CPU address space to the PCI address space.  There is one M32
92 	need to ensure Linux doesn't assign anything there, the M32 logic
115 	address on the PowerBus).  There is a way to also set the top 14
120 	has 256 segments; however, there is no table for mapping a segment
124 	there's a defined ordering for which window applies.
145       than one segment, we end up with more than one PE#.  There is a HW
186   There are several strategies for isolating VFs in PEs:
188   - M32 window: There's one M32 window, and it is split into 256
203     PEs (the segment number is the PE#), so there isn't as much
277   reserved in software; there are still only total_VFs VFs, and they only
278   respond to segments [0, total_VFs - 1].  There's nothing in hardware that
305 allocate 256 segments, there are (256 - numVFs) choices for the PE# of VF0.
311 space will consume (numVFs * n) segments.  That means there aren't as many