Lines Matching refs:dependency

55      - Data dependency barriers (historical).
190 There is an obvious data dependency here, as the value loaded into D depends on
395      dependency barriers; see the "SMP barrier pairing" subsection.
398  (2) Data dependency barriers.
400      A data dependency barrier is a weaker form of read barrier.  In the case
403      load will be directed), a data dependency barrier would be required to
407      A data dependency barrier is a partial ordering on interdependent loads
413      considered can then perceive.  A data dependency barrier issued by the CPU
418      dependency barrier.
423      [!] Note that the first load really has to have a _data_ dependency and
424      not a control dependency.  If the address for the second load is dependent
425      on the first load, but the dependency is through a conditional rather than
426      actually loading the address itself, then it's a _control_ dependency and
430      [!] Note that data dependency barriers should normally be paired with
436      A read barrier is a data dependency barrier plus a guarantee that all the
444      Read memory barriers imply data dependency barriers, and so can substitute
561 data-dependency barriers.
563 The usage requirements of data dependency barriers are a little subtle, and
576 There's a clear data dependency here, and it would seem that by the end of the
591 To deal with this, a data dependency barrier or better must be inserted
601 			      <data dependency barrier>
618 A data-dependency barrier is not required to order dependent writes
635 Therefore, no data-dependency barrier is required to order the read into
637 even without a data-dependency barrier:
642 of dependency ordering is to -prevent- writes to the data structure, along
648 Note well that the ordering provided by a data dependency is local to
653 The data dependency barrier is very important to the RCU system,
669 A load-load control dependency requires a full read memory barrier, not
670 simply a data dependency barrier to make it work correctly.  Consider the
675 		<data dependency barrier>  /* BUG: No data dependency!!! */
680 dependency, but rather a control dependency that the CPU may short-circuit
826 defeating control dependency:
862 A weakly ordered CPU would have no dependency of any sort between the load
870 Note well that the ordering provided by a control dependency is local
890       destroy the control dependency while respecting the letter of the
901       dependency into nonexistence.  Careful use of READ_ONCE() or
902       atomic{,64}_read() can help to preserve your control dependency.
906       of the if-statement containing the control dependency, including
909       control dependency.
930 with a data dependency barrier, a control dependency, an acquire barrier,
932 read barrier, control dependency, or a data dependency barrier pairs
951 			      <data dependency barrier>
961 			         <implicit control dependency>
971 match the loads after the read barrier or the data dependency barrier, and vice
1024 Secondly, data dependency barriers act as partial orderings on data-dependent
1070 If, however, a data dependency barrier were to be placed between the load of C
1081 				<data dependency barrier>
1295 Placing a read barrier or a data dependency barrier just before the second
1397 only the data dependency shown below:
1403 				<data dependency>	<read barrier>
1410 The key point is that although CPU 2's data dependency orders its load
1829 All memory barriers except the data dependency barriers imply a compiler
2434 CPU, that CPU's dependency ordering logic will take care of everything else.
2883 the data dependency barrier really becomes necessary as this synchronises both